静电注入对55nm MV/HV GGNMOS ESD性能的影响  

Effects of ESD IMP on ESD Performance of MV/HV GGNMOS

作　　者：王新泽 毛海央 金海波[3] 龙克文 WANG Xinze;MAO Haiyang;JIN Haibo;LONG Kewen(School of Microelectronics,University of Chinese Academy of Sciences,Beijing 1000029,P.R.China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,P.R.China;Semiconductor Manufacturing International Corporation,Beijing 100176.P.R.China;Foshan Chuandong Magnetic Electronic Co.,Ltd.,Foshan,Guangdong 528500,P.R.China)

机构地区：[1]中国科学院大学微电子学院,北京100029 [2]中国科学院微电子研究所,北京100029 [3]中芯国际集成电路制造有限公司,北京100176 [4]佛山市川东磁电股份有限公司,广东佛山528500

出　　处：《微电子学》2021年第1期132-136,共5页Microelectronics

基　　金：广东省重点领域研发计划项目(2019B010117001)。

摘　　要：静电防护问题是提升集成电路可靠性面临的主要挑战之一。基于55 nm HV CMOS工艺,研究了静电注入对中压(MV)和高压(HV)GGNMOS(Gate-Grounded NMOS)器件静电防护性能的影响。研究结果表明,对MV GGNMOS器件来说,静电注入能够在有效降低开启电压(V_(t))、保持电压(V_(h))的同时,减小对二次击穿电流(I_(t2))的影响,且注入面积的改变对器件性能的影响极为有限;对HV GGNMOS器件来说,提高静电注入浓度能够有效提高静电防护能力。ESD protection has always been one of the main challenges in improving reliability of integrated circuits. Based on a 55 nm HV CMOS process, the effects of electrostatic implantation(ESD IMP) on the performance of medium voltage(MV) and high voltage(HV) Gate-Grounded NMOS(GGNMOS) devices were studied. The results showed that for MV GGNMOS devices, the turn-on voltage(V_(t)) and hold voltage(V_(h)) were reduced by electrostatic implantation with a limited influence on the secondary breakdown current(I_(t2)), and the effect on device performance of implantation area was limited. For HV GGNMOS devices, the robustness of electrostatic protection was improved by increasing the electrostatic implantation concentration.

关 键 词：静电注入 静电防护 栅极接地NMOS 中压/高压 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN406