基于FPGA的H.264解码IP核中帧内预测模块的设计  

Design of Intra-prediction Module in H.264 Video Decoding IP Core on FPGA

作　　者：杨炎思 甘怡 YANG Yansi;GAN Yi(Jiangxi Radio and TV Station, Nanchang 330029, China)

机构地区：[1]江西广播电视台,江西南昌330029

出　　处：《中国有线电视》2021年第4期357-359,共3页China Digital Cable TV

摘　　要：提出了一种基于FPGA的H.264视频解码的IP核设计方案,对以NIOS II软件处理器为内核的SOPC系统进行了优化。对帧内预测进行了优化。帧内预测模块硬件加速的方法,与无硬件加速的NIOS II软件解码方法相比,缩短了解码耗时。该方法使基于FPGA的H.264视频实时解码和播放成为可能。This paper presents a design of IP core used in H.264 video decoding based on FPGA,which optimizes the SOPC system with NIOS II software processor being the kernel.This design contributes to the optimization of the intra-prediction module.The methodology of hardware acceleration to intra-prediction module,which compared to the decoding method exerted by NIOS II software without the assistance of hardware acceleration,shrinks the span of time consumed.The methodology makes it possible to realize the real-time H.264 video decoding and playing on FPGA.

关 键 词：H.264 NIOS II SOPC IP core Intra-prediction 

分 类 号：TN919.8[电子电信—通信与信息系统]