DrPlace:基于深度学习的可布线性驱动布局算法  

DrPlace:A Deep Learning Based Routability-Driven VLSI Placement Algorithm

作　　者：郝睿 蔡懿慈[1] 周强[1] 王锐[2] Hao Rui;Cai Yici;Zhou Qiang;Wang Rui(Department of Computer Science and Technology,Tsinghua University,Beijing 100084;School of Computer Science and Engineering,Beihang University,Beijing 100191)

机构地区：[1]清华大学计算机科学与技术系,北京100084 [2]北京航空航天大学计算机学院,北京100191

出　　处：《计算机辅助设计与图形学学报》2021年第4期624-631,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(61774091);国家重点研发计划(2019YFB2205001)。

摘　　要：在集成电路物理设计的布局阶段,针对基于深度学习的布局算法结果可布线性较差的问题,在开源的DREAMPlace算法的基础上提出并实现了一种基于深度学习的可布线性驱动布局算法DrPlace.算法模型在总体上设计并实现了布局器的整体框架,集成了基于深度学习的可布线性驱动总体布局、可布线性驱动的合法化和详细布局.总体布局过程中,在目标函数中加入了引脚密度函数,并实现了基于GPU的引脚密度的关键内核.在ISPD2011和DAC 2012布局实例上的实验结果表明,该算法与DREAMPlace相比在可布线性上获得了提升,且在运行时间、线长和可布线性方面均优于传统的可布线性驱动布局算法.In order to improve the routability of deep learning based placement algorithms in the VLSI physical design stage,on the basis of open source placement algorithm DREAMPlace,a deep learning based routability-driven VLSI placement algorithm named DrPlace is proposed.The framework of the algorithm model is composed of deep learning based routability-driven global placement,routability-driven legalization,and routability-driven detailed placement.The algorithm adds the pin density function into the global placement model and proposes an efficient GPU implementation of pin density key kernel.According to the experiment results on ISPD 2011 and DAC 2012 benchmark suites,the algorithm improves the routability of the DREAMPlace and is more effective than traditional routability-driven placement algorithms.

关 键 词：深度学习 布局 可布线性驱动 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]