基于FPGA的TCP段乱序重排设计与实现  

Design and Implementation of TCP Segment Reordering Based on FPGA

作　　者：黄锐[1] 王银[1] 杨宪伟[1] 李治辉[1] HUANG Rui;WANG Yin;YANG Xianwei;LI Zhihui(No.30 Institute of CETC,Chengdu 610041,China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《通信电源技术》2020年第24期67-69,73,共4页Telecom Power Technology

摘　　要：介绍一种基于FPGA的TCP段乱序重排设计与实现,记录乱序报文起止序号,通过并行比较确定新收报文的相对位置,将序号写入偏移缓存数据,完成乱序重排。该方法具有逻辑简单、处理效率高及资源消耗低的优点,测试表明以该方法实现的TCP硬件协议栈数据收发速率达到9.388 Gb/s。Introduces the design and implementation of segment reordering in a TCP hardware stack based on FPGA.The starting and ending sequence number of segment are recorded,the relative position of new segment is determined by parallel comparison with the existing record,write the data into buffer with the sequence number as offset,and complete the reordering.This method has the advantages of compact structure,high efficiency and low resource consumption,the test results show that the performance of TCP hardware protocol stack based on this method reaches 9.388 Gb/s.

关 键 词：FPGA TCP协议栈 乱序重排 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]