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作 者:孙欣欣 李娟[1] 田粉仙 杨军[1] SUN Xin-xin;LI Juan;TIAN Fen-xian;YANG Jun(School of Information Science&Engineering,Yunnan University,Kunming 650500,Yunnan,China)
出 处:《云南大学学报(自然科学版)》2021年第3期444-450,共7页Journal of Yunnan University(Natural Sciences Edition)
基 金:国家自然科学基金(11663007).
摘 要:针对目前卡板与主机系统之间存在数据传输过程中吞吐量过小,导致系统处理器速率慢的不足,提出了一种高性能的直接存储器访问(Direct Memory Access,DMA)引擎架构设计方案.首先,就改进后的分散聚集DMA传输模式提出了DMA单核引擎构架;然后,在兼容Xilinx FPGA 6、7系列的DMA单核引擎构架基础上提出了由两个PCIE IP核通过x8通道与PCIE桥并行使用的双核DMA引擎设计方案;最后,用Virtex-6 FPGA开发板对Xilinx PCIE Gen2进行DMA引擎性能测试.经测试,DMA单核引擎的吞吐量最高可达3721 MB/s,与此同时,双核引擎能达到6925 MB/s,约为单核引擎的2倍,达到了设计要求.该设计具有良好的稳定性,可广泛应用于卫星遥测、无人机入侵数据获取、雷达系统等高速数据采集系统.Aiming at the problem that the throughput between the card board and the host system is too small in the process of data transmission,the system processor speed is slow,and a high-performance Direct Memory Access(DMA)engine architecture design scheme is proposed.First,a DMA single-core engine architecture is proposed for the improved distributed aggregation DMA transmission mode.Then,based on the DMA single-core engine architecture compatible with Xilinx Field Programmable Gate Array(FPGA)6 and 7 series,it is proposed that two Peripheral Component Interconnect Express(PCIE)IP cores communicate with PCIE through x8 channels.The dual-core DMA engine design scheme used by the bridge in parallel.Finally,the Xilinx PCIE Gen2 is used to test the performance of the DMA engine with the Virtex-6 FPGA development board.After testing,the throughput of the DMA single-core engine can reach up to 3721 MB/s,at the same time,the dual-core engine can reach 6925 MB/s,which is about twice that of the single-core engine,meeting the design requirements.This design has good stability and can be widely used in high-speed data acquisition systems such as satellite telemetry,Unmanned Aerial Vehicle intrusion data acquisition and radar systems.
关 键 词:PCIE FPGA 直接存储器访问 高速数据传输
分 类 号:TP391[自动化与计算机技术—计算机应用技术]
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