基于FPGA的高速高效率数字下变频  

A high-speed and high-efficient digital down conversion based on FPGA

作　　者：戴曜泽 张棋 徐小淇 Dai Yaoze;Zhang Qi;Xu Xiaoqi(No.8511 Research Institute of CASIC,Nanjing 210007,Jiangsu,China)

机构地区：[1]中国航天科工集团8511研究所,江苏南京210007

出　　处：《航天电子对抗》2021年第2期47-51,共5页Aerospace Electronic Warfare

摘　　要：介绍了一种基于FPGA的高速高效数字下变频实现结构,该结构基于抽取器的等价原理,对数字下变频结构进行简化。通过理论推算分析,发现该结构可大幅度减少资源消耗和提高系统的处理速度,并通过FPGA仿真验证了理论和工程实现的一致性。A high-speed and high-efficient digital down conversion implementation structures based on FPGA is introduced.Based on the equivalence principle of the extractor,the structure simplifies the structure of the digital down conversion.Through theoretical calculation and analysis,it is found that this structure can greatly reduce the resource consumption and improve the processing speed of the system,and the consistency of theory and engineering implementation is verified by FPGA simulation.

关 键 词：数字下变频 抽取器 FPGA仿真 

分 类 号：TN97[电子电信—信号与信息处理]