2.5D硅转接板关键电参数测试技术研究  

Research on Key Electrical Parameters’ Testing Technology of 2.5D Silicon Interposer

作　　者：刘玉奎[1] 崔伟[1,2] 毛儒焱[1] 孙士[3] 殷万军 LIU Yukui;CUI Wei;MAO Ruyan;SUN Shi;YIN Wanjun(The 24th Institute of China Ele.Technol.Group Corp.,Chongqing 400060,P.R.China;Sci.and Technol.on Analog Integr.Cire.Lab.,Chongqing 400060,P.R.China;.3.Chongqing Southuest IC Design Co.,Ltd.,Chongqing 400060,P.R.China)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路国家重点实验室,重庆400060 [3]重庆西南集成电路设计有限责任公司,重庆400060

出　　处：《微电子学》2021年第2期270-275,共6页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(6142802190502)。

摘　　要：硅转接板是3D IC中实现高密度集成的关键模块,获取其技术参数对微系统的设计至关重要。以实际研制的一种2.5D硅转接板为研究对象,对大马士革铜布线(Cu-RDL)、硅通孔(TSV)关键电参数的测试结构与测试方法进行了研究,并对TSV电参数测试结构的寄生电容进行了分析。研究结果表明,研制的2.5D硅转接板中10μm×80μm TSV的单孔电阻为26 mΩ,1.7μm厚度的Cu-RDL的方块电阻为9.4 mΩ/,测试结果与理论计算值相吻合。本研究工作为2.5D/3D集成工艺的研发和建模提供了基础技术支撑。The silicon interposer is the key module for 3 D IC to achieve higher integration density. Obtaining its technical parameters is crucial to the design of the micro-system. An actually developed 2.5 D silicon interposer was took as the research object. The key electrical parameters’ testing technology of Damascus copper redistribution layer(Cu-RDL) and through silicon via(TSV) were studied, and TSV parasitic capacitance was analyzed. The research results showed that the resistance of 10 μm×80 μm single hole TSV developed in 2.5 D silicon interposer was 26 mΩ, and the sheet resistance of the Cu-RDL with a thickness of 1.7 μm was 9.4 mΩ/□. The measured results were consistent with that of theoretical calculations. This research work provided a basic technical support for the development and modeling of 2.5 D/3 D integrated process.

关 键 词：2.5D硅转接板 铜再布线 硅通孔 电阻测试 3D集成电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]