DMR:兼容RISC-V架构的乱序超标量通用处理器核  

DMR:An Out-of-Order Superscalar General-Purpose CPU Core Based on RISC-V

作　　者：孙彩霞[1] 郑重[1] 邓全[1] 隋兵才[1] 王永文[1] 倪晓强[1] Sun Caixia;Zheng Zhong;Deng Quan;Sui Bingcai;Wang Yongwen;Ni Xiaoqiang(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073)

机构地区：[1]国防科技大学计算机学院,长沙410073

出　　处：《计算机研究与发展》2021年第6期1230-1233,共4页Journal of Computer Research and Development

基　　金：广东省重点领域研发计划(2019B121204007)。

摘　　要：DMR是由国防科技大学计算机学院自研的一款兼容RISC-V架构的乱序超标量通用处理器核,支持用户态(user-mode)、特权态(supervisor-mode)和机器态(machine-mode)三种特权级模式,兼容RV64G指令集规范,并进行了自定义向量扩展,虚存系统支持Sv39和Sv48,物理地址为44b.DMR的单周期整数流水线为12级,指令乱序发射、顺序提交,指令发射宽度为4,实现了多个分布式调度队列,每拍最多可乱序调度9条指令执行.DMR采用覆盖率驱动的多层次、多平台的功能验证方法,已经在FPGA原型系统下成功启动Linux OS,CoreMark分数为5.12MHz,在14nm工艺下主频可达到2GHz.DMR is a RISC-V based out-of-order superscalar general-purpose CPU core from the College of Computer Science and Technology,National University of Defense Technology.Three privilege levels,user-mode,supervisor-mode and machine-mode,are all supported,and the standard RISC-V RV64G instruction set is implemented.In addition,custom vector instructions are extended in DMR.Sv39 and Sv48 are supported for the virtual-memory system,and the size of physical address is 44-bit.The pipeline for single-cycle integer instructions is 12-stage in all.All instructions are executed out of program order and committed in program order.More than four instructions can be issued per cycle.Distributed schedule queues are used and at most 9 instructions can be out-of-order scheduled for executions in one cycle.Multi-layer,multi-platform functional verification method driven by functional coverage is used,and Linux OS is already booted on FPGA prototype system.DMR reaches 5.12CoreMarkMHz and targets 2GHz clock speed in 14nm technology.

关 键 词：RISC-V 乱序 超标量 处理器核 通用CPU 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]