基于Platform Designer的自定义等精度测频IP核设计方案  

The Solution of Self-Defined Equal Precision Frequency Measurement IP Core Based on Platform Designer

作　　者：陈皓 刘三军 CHEN Hao;LIU Sanjun(School of Information Engineering,Hubei Minzu University,Enshi Hubei 445000,China)

机构地区：[1]湖北民族大学信息工程学院,湖北恩施445000

出　　处：《信息与电脑》2021年第7期48-51,共4页Information & Computer

基　　金：国家自然科学基金“CCFD非线性自干扰模型及高抑制比技术研究”(项目编号:61961016);湖北省自然科学基金“5G同频同时全双工(CCFD)自干扰消除模型研究”(项目编号:2019CFB593);湖北民族大学博士科研启动基金项目“针对OFDM数字基带发生器的IFFT处理器”(项目编号:MY2018B08)。

摘　　要：笔者运用FPGA技术,通过使用开发工具Platform Designer,给出一种拥有Avalon总线接口、实现等精度测频功能的自定义IP(Intellectual Property,知识产权)核的设计方案。不但能解决传统测频方法存在的±1误差问题,还能轻易实现单路或多路同时进行等精度测频,待测信号的最低频率可低至0.5 Hz,最高频率可高达200 MHz。测试结果表明,系统的测频精度可达到10-8。本文给出基于Avalon总线的等精度测频IP核的设计思想、封装流程以及利用Nios II处理器进行访问控制的方法,用户只需要通过双击鼠标的方式即可将该IP核轻松地挂接到SOPC系统中,具有超佳的灵活性和便捷性,可广泛应用于多路测频、仪器设计、自动控制等领域。In this paper,an Intellectual Property core with Avalon bus interface is designed by using FPGA technology Platform Designer.It can not only solve the problem of±1 error in the traditional frequency measurement method,but also easily realize high precision frequency measurement by single or multiple channels simultaneously.The lowest frequency of the signal to be measured can be as low as 0.5 Hz,and the highest frequency can be as high as 200 MHz,the theoretical and experimental results show that the frequency measurement accuracy of the system can reach 10-8.This paper presents the design idea,encapsulation process and access control method using Nios II processor of the same precision frequency measurement IP core based on Avalon bus,users can easily hook up the IP core to SOPC system by double-clicking the mouse,which has excellent flexibility and convenience,and can be widely used in the fields of multi-channel frequency measurement,instrument design,automatic control and so on.

关 键 词：SOPC系统 自定义IP核 等精度 

分 类 号：TM935.13[电气工程—电力电子与电力传动]