基于FPGA的多端口网络协议解析加速卡硬件电路设计  

Hardware Circuit Design of Network Acceleration Card based on FPGA

作　　者：卞中昊 田野 司艺 朱超 BIAN Zhonghao;TIAN Ye;SI Yi;ZHU Chao(No.3 Institute of Ministry of Public Security,Shanghai 200031,China;China Information Communication Technology Group Co.,Ltd.,Wuhan Hubei 430074,China;Shanghai Information Management Network Technology Co.,Ltd.,Shanghai 200032,China;Shanghai Feikuan Communication Technology Co.,Ltd.,Shanghai 200240,China)

机构地区：[1]公安部第三研究所,上海200031 [2]中国信息通信科技集团有限公司,湖北武汉430074 [3]上海信管网络科技有限公司,上海200032 [4]上海飞宽通信技术有限公司,上海200240

出　　处：《通信技术》2021年第6期1521-1528,共8页Communications Technology

摘　　要：为了实现多通道网络协议快速分析,设计了一款基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的PCIe Gen3接口硬件板卡FBC-810x,用于服务器以及数据中心的网络协议解析加速。硬件上是由PCIe Gen3×16以及4个通道的QSFP28100 Gb/s串行通信的光模块接口堆叠而成,使用了Xilinx公司的Zynq UltraScale+器件,硬件最高支持400 Gb/s的网络加速卡。设计了400 Gb/s网络加速卡系统、时钟以及电源的方案,并对球状矩阵排列(Ball Grid Array,BGA)芯片扇出至PCIe端以及QSFP28光模块端传输线进行仿真,验证了设计可以满足高速信号的传输需求。In order to realize the fast analysis of multi-channel network protocol,a FPGA based hardware board(FBC-810x)of PCIe Gen3 interface is designed to accelerate network protocol resolution of servers and data centers.The hardware is composed of PCIe Gen3×16 and 4 channels of QSFP28100 Gb/s serial communication optical module interface stack,and uses Xilinx Company’s Zynq UltraScale+device.The hardware supports up to 400 Gb/s network accelerator cards.This paper designs a 400 Gb/s network accelerator card system,clock and power supply scheme,and simulates the BGA chip fan out to the PCIe end and the QSFP28 optical module end transmission line,which verifies that the design can meet the needs of high-speed signal transmission.

关 键 词：400 Gb/s网络加速卡 信号完整性 PCIE QSFP28 S参数 

分 类 号：TN929.1[电子电信—通信与信息系统]