基于FPGA的LVDS无时钟数据传输方案设计与实现  

Design and implementation of LVDS clockless data transmission scheme based on FPGA

作　　者：毕彦峰 李杰[1] 胡陈君 Bi Yanfeng;Li Jie;Hu Chenjun(State Key Laboratory of Electronic Testing Technology,North University of China,Taiyuan 030051,China;Suzhou Zhongsheng Nanotechnology Company,Suzhou 215123,China)

机构地区：[1]中北大学电子测试技术重点实验室,山西太原030051 [2]苏州中盛纳米科技有限公司,江苏苏州215123

出　　处：《电子技术应用》2021年第6期62-66,共5页Application of Electronic Technique

基　　金：国家自然科学基金(61973280)。

摘　　要：针对离线式弹载数据采集存储设备小型化需求,设计了一种基于FPGA的LVDS(Low-Voltage Differential Signaling)无时钟高速数据传输系统。在不外挂接口芯片的情况下,用板载时钟代替差分时钟,仅使用一对差分管脚即可完成一路LVDS无时钟数据传输,系统中数据接口较多时可以很大程度上减少板卡体积。通过提高FPGA内部SERDES(Serializer-Deserializer)反串行化比例以及数据进行8B/10B编码解决鉴相器失效的问题,并以此为板载时钟提供准确的相位信息来对齐串行数据和模拟时钟,最后按照模拟时钟将串行LVDS数据反序列化,从而达到板载时钟代替LVDS随路时钟的目的,以此实现基于FPGA无随路时钟的LVDS高速传输。试验表明,该系统能够可靠、有效工作,具备一定工程实用价值。Aiming at the miniaturization requirements of off-line bomb-borne data acquisition and storage equipment,an FPGA-based LVDS clockless high-speed data transmission system is designed.Without an external interface chip,the onboard clock is used to replace the differential clock,and only a pair of differential pins can complete a LVDS clockless data transmission.When there are many data interfaces in the system,the board volume can be greatly reduced.The problem of phase detector failure is solved by increasing the deserialization ratio of the FPGA internal SERDES and 8B/10B encoding of the data,so to provide accurate phase information for the onboard clock to align the serial data and the analog clock.Finally,following the analog clock,the serial LVDS data is deserialized,so as to achieve the purpose of replacing the LVDS accompanying clock with the onboard clock,so as to achieve high-speed LVDS transmission based on FPGA without accompanying clock.Tests show that the system can work reliably and effectively,and has certain engineering practical value.

关 键 词：FPGA 无时钟传输 LVDS SERDES 

分 类 号：TN919[电子电信—通信与信息系统] TP274[电子电信—信息与通信工程]