基于FPGA的SoC接口在CNN加速器中的研究  

Research on FPGA-based SoC interface in CNN accelerator

作　　者：夏冰洁 王琴[1] XIA Bingjie;WANG Qin(School of Electronic Information and Electrical Engineering,Shanghai Jiaotong University,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《电子设计工程》2021年第12期6-8,13,共4页Electronic Design Engineering

基　　金：国家自然科学基金项目(61176037)。

摘　　要：卷积神经网络计算的显著特点在于计算的数据量大、计算过程繁杂、数据流动复杂,基于这些特点,为了实现一种较为高效的卷积神经网络数据传输,设计了一条从外围存储设备中读写数据,进入计算模块的通路。以“SPIFlash-DDR-计算模块”为主要数据通路,并引入PingPong读写操作进行数据流优化,结合Vivado仿真平台进行综合分析,最终实现了100 MHz时钟频率的数据通路,并给出了每层卷积数据大致的输入时间。The conspicious features of convolutional neural network calculations are the large amount of calculated data,complex calculation process,and complex data flow.Based on these characteristics,in order to achieve a more efficient convolutional neural network data transmission purpose,a peripheral storage device is designed.The data to be read and writen enters the path of the computing module.Through the use of"SPI Flash-DDR-computing module"as the main data path and the introduction of PingPong read and write operations for data flow optimization,combined with the analysis and synthesis of the Vivado simulation platform,a data path with a clock frequency of 100 MHz is finally realized,and approximate input time of data of each layer is provided.

关 键 词：SoC接口 DMA接口设计 CNN加速器 FPGA 

分 类 号：TN492[电子电信—微电子学与固体电子学]