面向100 Gbps网络应用的RISC-V CPU设计与实现  

Design of RISC-V CPU for 100 Gbps Network Application

作　　者：李晓霖 韩萌 郝凯 薛海韵[5] 卢圣健 张昆明 祁楠 牛星茂 肖利民[3] 郝沁汾[1,2] Li Xiaolin;Han Meng;Hao Kai;Xue Haiyun;Lu Shengjian;Zhang Kunming;Qi Nan;Niu Xingmao;Xiao Limin;Hao Qinfen(High-Throughput Computer Research Center,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049;School of Computer Science and Engineering,Beihang University,Beijing 100191;State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083;SiP Center,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029)

机构地区：[1]中国科学院计算技术研究所高通量计算机研究中心,北京100190 [2]中国科学院大学计算机科学与技术学院,北京100049 [3]北京航空航天大学计算机科学与工程学院,北京100191 [4]中国科学院半导体研究所超晶格国家重点实验室,北京100083 [5]中国科学院微电子研究所系统封装与集成研发中心,北京100029

出　　处：《计算机辅助设计与图形学学报》2021年第6期956-962,共7页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家重点研发计划(2019YFB2203004);北京市科技计划(Z191100004819006).

摘　　要：RISC-V作为新一代开源精简指令集,具有功耗低、面积小和性能高的优点,因此基于RISC-V架构的技术和产品发展迅速.然而,目前基于RISC-V架构的中高端64位CPU设计实例很少,也缺乏相应的商用IP,尤其是在面向高速网络应用方面.因此,首先改进了开源的64位U500 RISC-V SoC,包括增加了总线宽度和集成二级缓存等;然后在CPU中实现了完整的100 Gbps以太网功能模块,包括介质访问控制子层、物理编码子层和串行器/解串器以及用于该功能模块的发送缓冲区和接收缓冲区;最后通过前端仿真、FPGA验证以及启动Linux操作系统,验证了所设计的64位RISC-V CPU以及100 Gbps以太网功能模块的正确性和有效性.所设计的RISC-V CPU和100 Gbps以太网功能模块可应用于智能网卡等数据中心应用场景.As a new open-source reduced instruction set architecture,RISC-V has advantages of low power consumption,small area and high performance.Therefore,technology and products based on RISC-V are de-veloping rapidly.However,currently there are few medium and high end 64 bit CPU design instances based on the RISC-V architecture,and it is also hard to find corresponding commercial IP,especially for high-speed network applications.In this paper,we firstly improved the open source 64 bit U500 RISC-V SoC by extending the Bus width and adding L_(2)Cache,and etc.Secondly we implemented a complete 100 Gbps Ethernet func-tion,which includes MAC,PCS,and SerDes,and the TX buffer and RX buffer used for the function.Finally we proved correctness and effectiveness of entire 64 bit RISC-V CPU design and 100 Gbps Ethernet function by simulation,FPGA verification and boot of Linux operation system.The designed RISC-V CPU and 100 Gbps Ethernet function can be applied to data center application such as smart network interface cards.

关 键 词：RISC-V 片上系统 100 Gbps以太网 介质访问控制子层 物理编码子层 串行器/解串器 智能网卡 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]