吉赫兹DAC测试电路的设计与实现  

Design and Implementation of Test Circuit for Gigahertz DAC

作　　者：邱丹 苏小波[1] 王祖锦 朱夏冰 Qiu Dan;Su Xiao-bo;Wang Zu-jin;Zhu Xia-bing(China electronics Technology Group Corporation No.58 Research Institute,Jiangsu Wuxi 214035)

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子质量》2021年第6期15-19,共5页Electronics Quality

摘　　要：设计并实现了应用于2.8 G高速DAC芯片的内部测试电路,该电路输出两路线性斜坡信号作为DAC模块的输入数据,DAC模块将其合成为一路线性斜坡信号输出。通过设计实验和多种设计方案优缺点比较,该测试电路最终采用两路并行累加器架构,克服了传统累加器结构无法用于高速电路的固有缺陷。在65 nm工艺下,基于此测试电路设计了测试芯片并进行了流片验证。测试结果表明:测试芯片整体可达到2.8 G SPS的测试速度,实现了对吉赫兹DAC全扫描测试的设计目标。Designed and implemented internal test circuit for 2.8 G high-speed DAC chip,which outputs twolinear ramp signals as input data for DAC block,and DAC block synthesize these two signals into one linearramp signal as output.By design experiments and comparison of merits and drawbacks of several designschemes,the test circuit employs 2-parallel accumulator architecture eventually,which overcomes the intrinsicshortcoming of traditional accumulator structure that cannot be used for high-speed circuit.At 65 nm techno-logy,test chip was designed based on this test circuit and verified.The test result shows that the test chipreaches 2.8 G sample-per-second test speed as a whole,and the design goal that do full-scan test togigahertz DAC is achieved.

关 键 词：高速DAC 测试电路 并行累加器 

分 类 号：TN407[电子电信—微电子学与固体电子学]