雷达自适应副瓣对消的FPGA工程实现  

FPGA Implementation of Adaptive Sidelobe Cancellation for Radar

作　　者：王佳鑫[1] WANG Jiaxin(China Electronic Technology Group Corporation twentyth Institute,Xi'an 710068,China)

机构地区：[1]中国电子科技集团公司第二十研究所,陕西西安710068

出　　处：《通信电源技术》2021年第5期24-27,共4页Telecom Power Technology

摘　　要：抗干扰能力已成为雷达电子对抗技术的重要指标。在众多抗干扰技术中,副瓣对消是其中一个重要手段,用于消除从天线副瓣进入的干扰信号。为了提高传统处理器的计算效率,介绍了一种自适应副瓣对消在可编程逻辑器件(Field Programmable Gate Array,FPGA)中的实现方法,具有更好的实时性。基于某相控阵雷达测试了该方法的有效性和实时性,并对比了在不同辅助通道数和干扰点数下的副瓣对消效果。The anti-jamming ability has become an important technical index of radar electronic countermeasure.In many anti-jamming technologies,sidelobe cancellation is one of the important means,which is used to eliminate the interference signal of antenna sidelobe.In order to improve the computational efficiency of traditional processors,this paper introduces an implementation method of adaptive sidelobe cancellation in programmable logic device(FPGA),which has better real-time performance.Based on a phased array radar,the effectiveness and real-time performance of the method are tested,and the sidelobe cancellation effects under different auxiliary channels and jamming points are compared.

关 键 词：相控阵雷达 自适应副瓣对消 FPGA 

分 类 号：TN9[电子电信—信息与通信工程]