基于多核处理器BWDSP1042的FFT性能优化  

Optimization of FFT Performance Based on BWDSP1042

作　　者：蔺丽华[1] 李敏 苏涛[2] 张美春 王佳仪 LIN Lihua;LI Min;SU Tao;ZHANG Meichun;WANG Jiayi(College of Communication and Information Engineering,Xi′an University of Science and Technology,Xi′an 710054,China;State Key Laboratory of Radar Signal Processing,Xidian University,Xi′an 710126,China)

机构地区：[1]西安科技大学通信与信息工程学院,西安710054 [2]西安电子科技大学雷达信号处理国家重点实验室,西安710126

出　　处：《电讯技术》2021年第6期759-764,共6页Telecommunication Engineering

基　　金：国家科技重大专项(2012ZX01034001-001)。

摘　　要：博微DSP1042(BWDSP1042)是我国自主研发的一款高性能数字信号处理器。现阶段,由于BWDSP硬件计算资源和访存带宽限制,通过调优快速傅里叶变换(Fast Fourier Transform,FFT)算法结构运算时间仍可减少。基于高性能多核BWDSP1042体系架构以及指令编排原则,优化了基-2FFT算法结构,在充分利用硬件资源的同时减少了FFT算法的运算时间。使用Matlab程序验证FFT汇编算法的正确性,并与BWDSP100、C6678函数库中的FFT算法的实际运行周期进行对比。研究结果表明,512点、1024点、2048点定点复数FFT算法的运算时间比BWDSP100函数库中的FFT和C6678函数库中的FFT均缩短了一倍多。Bo Wei DSP1042(BWDSP1042)is a high-performance digital signal processor independently developed by China.At present,due to the limitations of BWDSP hardware computing resources and memory access bandwidth,the calculation time can still be reduced by tuning the fast Fourier transform(FFT)algorithm structure.This paper optimizes the radix-2 FFT algorithm structure based on the high-performance multi-core BWDSP1042 architecture and instruction scheduling principles.While making full use of hardware resources,the calculation time of the FFT algorithm is reduced.Matlab program is used to verify the correctness of the FFT assembly algorithm,and it is compared with the actual operating cycle of the FFT algorithm in the BWDSP100 and C6678 function libraries.The research results show that the calculation time of the 512-point,1024-point,and 2048-point fixed-point complex FFT algorithm is more than twice as fast as the FFT in the BWDSP100 library and the FFT in the C6678 library.

关 键 词：数字信号处理 BWDSP1042 快速傅里叶变换 运算时间 

分 类 号：TN911.72[电子电信—通信与信息系统]