一种抑制选通器耐受性退化的两步写入方法  

Two-Step Write Scheme to Mitigate Endurance Degradation of the Selector

作　　者：李雨佳 唐建石 高滨[2,3] 许峰 李辛毅[2] 张万荣 吴华强[2,3] 钱鹤[2,3] Li Yujia;Tang Jianshi;Gao Bin;Xu Feng;Li Xinyi;Zhang Wanrong;Wu Huaqiang;Qian He(Faculty of Information Technology,Beijing University of Technology,Beijing 100124,China;Institute of Microelectronics,Beijing National Research Center for Information Science and Technology(BNRist),Tsinghua University,Beijing 100084,China;Beijing Innovation Center for Future Chips(ICFC),Tsinghua University,Beijing 100084,China)

机构地区：[1]北京工业大学信息学部,北京100124 [2]清华大学北京信息科学与技术国家研究中心微电子研究所,北京100084 [3]清华大学北京未来芯片高精尖中心,北京100084

出　　处：《半导体技术》2021年第6期434-439,共6页Semiconductor Technology

基　　金：国家重点研发计划资助项目(2016YFA0201800);国家自然科学基金资助项目(61974081,91964104)。

摘　　要：为了抑制选通-阻变(1S1R)交叉结构阵列在写操作过程中存在的选通器耐受性退化,对施加不同脉冲幅值和宽度的写入电压时HfO_(2)/Ag纳米点阈值开关选通器件的耐受性退化情况进行了测试和分子动力学模拟。结果表明,随着写入电压幅值和脉冲宽度的增加,选通器耐受性下降。基于此结果,提出一种将选通器开启过程和阻变存储器写过程分开操作的1S1R阵列两步写入方法来降低写过程中选通器上的分压,抑制选通器耐受性的退化。仿真和测试结果表明,相较于一步写操作方法,采用两步写入方法后,选通器件耐受性提高了一个数量级。此外,采用两步写入方法后,阵列能耗可降低58%以上,有利于大规模阵列的应用。In order to mitigate endurance degradation of the selector during write operation of the one-selector-one-resistor(1 S1 R)crossbar array,the endurance degradation of the HfO_(2)/Ag nanodots threshold switch based selector under write voltages with different pulse amplitudes and widths was tested and simulated by molecular dynamics.It is found that the endurance of the selector degrades as the amplitude and pulse width of the write voltage increases.Based on this result,a two-step write scheme that separated the processes of turning on selector and writing resistive random-access memory was proposed to enhance the endurance of the selector by reducing the operation voltage on the selector.Simulation and test results indicate that this two-step write scheme can improve the endurance of the selector by an order of magnitude compared with the one-step write scheme.Moreover,the energy consumption of the array can also be reduced by more than 58%by using the two-step write scheme,which is beneficial to the application of large-scale array.

关 键 词：选通器 耐受性退化 选通-阻变(1S1R)交叉结构阵列 写入方法 能耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]