The investigation of DARC etch back in DRAM capacitor oxide mask opening  

作　　者：Jianqiu Hou Zengwen Hu Kuowen Lai Yule Sun Bo Shao Chunyang Wang Xinran Liu Karson Liu 

机构地区：[1]Advanced Micro-Fabrication Equipment Inc.China,Shanghai 201201,China [2]ChangXin Memory Technologies Inc.,Hefei 230093,China

出　　处：《Journal of Semiconductors》2021年第7期88-92,共5页半导体学报（英文版）

摘　　要：Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70%mean-while resolve the DARC remain issue.We also found that CH_(2)F_(2) flow should be~15 sccm to avoid reversed CD trend and keep in-line CD.

关 键 词：dynamic random access memory(DRAM) oxide mask open of capacitor capacitive coupled plasma(CCP)etch dielectric anti-reflective coating(DARC) etch back(EB) 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]