基于四路ADC芯片交替采样的宽带信号采集系统设计  

Design of a Sampling System Based on Four-Channel ADC Chip Time-Interleaved Sampling

作　　者：雷雯 栗敬雨 LEI Wen;LI Jingyu(Naval Representative′s Office in Xiangtan,Xiangtan 411100,China;College of Advanced Interdisciplinary Studies, National University of Defense Technology,Changsha 410073,China)

机构地区：[1]海军驻湘潭地区军事代表室,湖南湘潭411100 [2]国防科技大学前沿交叉学科学院,湖南长沙410073

出　　处：《电子科技》2021年第9期30-35,共6页Electronic Science and Technology

基　　金：国家自然科学基金(61571449)。

摘　　要：高速高精度大带宽的信号采集系统是宽带成像雷达的重要组成部分。针对单片高精度ADC的采样率无法满足大带宽成像雷达中频直接采样的问题,文中采用多路ADC芯片交替采样的方法,在保持采样精度不变的条件下提升系统采样率。设计了一种基于4片ADC12DJ3200交替采样的宽带信号采集系统,该系统中ADC单片采样率为3.4 GS·s^(-1),合成的总采样率为13.6 GS·s^(-1),量化位数12 bit。测试结果表明,在440 MHz到6140 MHz频率范围内,该系统的有效位大于7.2 bit,无杂散动态范围大于51 dB。Signal sampling system with high speed,high precision and wideband is an important part of wideband imaging radar.For the problem that the sampling rate of single high-precision ADC chip cannot meet the direct intermediate frequency sampling of wideband imaging radar,the method of multiple ADC chips time-interleaved sampling is adopted in this study,which improves the sampling rate of the system under the condition of keeping the sampling accuracy unchanged.Four ADC12DJ3200 chips with a sampling rate of 3.4 GS·s^(-1) are used to design a wideband TIADC system with a total sampling rate of 13.6 GS·s^(-1),and the number of quantization bits is 12 bit.The test results show that in the frequency range of 440~6140 MHz,the effective number of bits and spurious free dynamic range of the system are more than 7.2 bit and 51 dB,respectively.

关 键 词：模数转换器 交替采样 宽带雷达 数字接收机 采集系统 电路设计 宽带信号 采样性能 

分 类 号：TN98[电子电信—信息与通信工程]