一种速度可扩展的时间交织复位运放流水线ADC的设计  

Design of A Speed Scalable Time-Interleaved Reset-Opamp Pipelined ADC

作　　者：乐丽琴[1] 贺素霞[1] 周湘贞 YUE Liqin;HE Suxia;ZHOU Xiangzhen(Faculty of Engineering,Huanghe Science and Technology University,Zhengzhou He’nan 450063,China;School of Computer Science and Engineering,Beihang University,Beijing 100191,China;Department of Information Engineering,Shengda Economics Trade&Management College of Zhengzhou,Zhengzhou He’nan 451191,China)

机构地区：[1]黄河科技学院工学部,河南郑州450063 [2]北京航空航天大学计算机学院,北京100191 [3]郑州升达经贸管理学院信息工程系,河南郑州451191

出　　处：《电子器件》2021年第3期539-546,共8页Chinese Journal of Electron Devices

基　　金：国家自然科学基金面上项目(61672077);河南省重点研发与推广专项支持项目(182102110277);河南省科技攻关项目(172102210379);郑州市重点实验室项目(郑科[2017]91号)。

摘　　要：本文提出了一种采用0.18μm CMOS工艺和金属-绝缘体-金属电容器选择的1.2 V、10位、60 Msample/s~360 Msample/s六通道的时间交织复位运放流水线ADC的设计。具体实现包括:采用一种前端电阻-解复用技术来实现6个时间交织通道和低压增益以及偏移补偿技术来减轻时间交织通道间的偏移失配;设计了反馈电流偏置来确保工艺变化过程中电流源偏置的精确性;设计了低电压电流模式子ADC来降低静态功耗;设计了一种可编程时序偏差不敏感时钟发生器来减轻不同通道之间的时序失配。芯片测试结果表明,对于全部速度选项来说,ADC的微分非线性/积分非线性优于0.8 LSB/1.1 LSB,且信噪失真比在55 dB以上,而在60 Msample/s和360 Msample/s时分别消耗83.2 mW和406 mW,整个ADC核面积仅为12.6 mm^(2)。In this paper,a 1.2 V,10 bit,60 Msample/s~360 Msample/s six channels time-interleaved reset-opamp pipelined ADC design is implemented in 0.18 CMOS process and metal-insulator-metal capacitor option.The concrete implements are included.A front-end resistive-demultiplexing technique is used to implement six time-interleaved channels and low voltage gain and offset compensation techniques are used to alleviate the offset-mismatch among the time-interleaved channels.Feedback current biasing is designed to ensure the accuracy of the current source biasing over the process variations.Low-voltage current-mode sub-ADCs are designed to reduce the static power consumption.A programmable timing-skew insensitive clock generator is designed to alleviates the timing-mismatches among different channels.The chip test results show that the ADC exhibits a differential non-linearity/integral non-linearity better than 0.8 LSB/1.1 LSB,and the signal-to-noise distortion ratio is above 55 dB for all speed options,while consuming 83.2 mW at 60 Msample/s and 406 mW at 360 Msample/s,respectively.The total ADC core area is only 12.6 mm^(2).

关 键 词：模数变换器 时间交织 解复用技术 偏移补偿 功耗 信噪失真比 

分 类 号：TN792[电子电信—电路与系统] TM935[电气工程—电力电子与电力传动]