面向NAND闪存的高能效LDPC译码器结构设计  

High Energy-Efficiency LDPC Decoder Architecture Design for NAND Flash Memory

作　　者：张超[1] 何卫锋[1] ZHANG Chao;HE Weifeng(Department of Microelectronics and Nanoscience,Shanghai Jiao Tong University,Shanghai 200240)

机构地区：[1]上海交通大学微纳电子学系,上海200240

出　　处：《现代计算机》2021年第17期75-80,共6页Modern Computer

摘　　要：LDPC码纠错性能极佳,可作为NAND闪存数据的新型纠错编码方案。然而,传统基于最大迭代周期来确定译码器处理速度的保守设计方法,降低译码电路的处理能效。基于这个问题一种自适应电压频率调节的高能效LDPC译码器结构被提出,该结构能够动态地调节译码器的工作频率和电压,使得电路在满足实时性能需求的同时降低处理能耗。在此基础上,采用28nm工艺完成LDPC译码器的逻辑综合。实验结果表明,不同信道噪声下译码器的功耗能够降低24.7%-61.4%,能效提升1.3-2.5倍。LDPC codes have excellent error correction performance and can be used as a new data error correction coding scheme for NAND flash.However,the conventional and conservative design method of determining the processing performance of the decoder based on maximum iterations reduces the processing energy efficiency of the decoding circuit. Based on this,a high energy-efficiency LDPC decoder architecture with Adaptive Voltage-Frequency Scaling( AVFS) scheme is proposed. This structure can dynamically adjust decoder’s work frequency and voltage,so that the circuit can reduce processing energy consumption while meeting real-time performance requirements. On this basis,the logic synthesis of the LDPC decoder is completed with 28 nm process. Experimental results show that the power consumption of the decoder can be reduced by 25%-62% and energy efficiency can be increased to 1. 3-2. 5 times under different AWGN noise.

关 键 词：QC-LDPC码 NMSA译码算法 LDPC译码器架构 自适应电压频率调节 高能效 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]