忆阻器的三值逻辑门和加法器设计  

Design of ternary logic gates and adder based on memristor

作　　者：钟悦航 武继刚[1] 刘鹏 姚廉 ZHONG Yuehang;WU Jigang;LIU Peng;YAO Lian(Guangdong University of Technology,Guangzhou 510006,China)

机构地区：[1]广东工业大学计算机学院,广东广州510006

出　　处：《微电子学与计算机》2021年第7期60-66,共7页Microelectronics & Computer

基　　金：计算机体系结构国家重点实验室开放课题(CARCH201907);广东省基础与应用基础研究基金(2019A1515110284)。

摘　　要：现有忆阻器的三值逻辑电路设计中无法级联且无法保存输入输出值,导致面积开销和功耗增加.通过对忆阻器辅助逻辑进行扩展,设计了忆阻器的三值逻辑门,具备三值逻辑的完备性.在此基础上设计实现了三值译码器和三值加法器.使用Spice仿真软件对所设计的电路进行了验证.结果表明:与已有的文献进行比较,所提出的电路面积和功耗有所减少.The existing ternary logic circuit of memristors cannot be cascaded and cannot store input and output values,which leads to the increase of area overhead and power consumption.Considering the characteristics of memristors and ternary logic,several ternary logic gates extended from MAGIC-Memristor-Aided Logic are proposed.Starting with the basic ternary logic gates,the ternary decoder and the ternary adder are realized.The circuit was verified by SPICE simulation software.The results show that the proposed circuit area overhead and power consumption are reduced compared with the existing literatures.

关 键 词：忆阻器 三值逻辑 加法器 SPICE 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]