一款8 bit 480MS/s逐次逼近型模数转换器  

An 8 bit 480MS/s SAR ADC

作　　者：吴琪 张润曦[1] 石春琦[1] WU Qi;ZHANG Runxi;SHI Chunqi(Institute of Microelectronic Circuit and System,East China Normal University,Shanghai,200062,CHN)

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062

出　　处：《固体电子学研究与进展》2021年第3期210-216,228,共8页Research & Progress of SSE

摘　　要：介绍了一款采用55 nm CMOS工艺设计的单通道8 bit 480 MS/s逐次逼近型模数转换器(SAR ADC)。采用数据环与异步时钟环的双环结构作为高速SAR ADC的系统框架。提出一种带有复位开关的动态比较器,缩短复位时间,提高比较精度。结合反向单调切换时序,减缓因输入共模电压降低而引起的比较器速度下降,提高ADC工作速度。芯片测试结果表明:在1.2 V电源电压时,ADC消耗6.9 mA的电流;在100 MHz输入条件下,实现147.3 dB的FOMS值,信噪失真比(SNDR)为42.7 dB,无杂散动态范围(SFDR)为50.53 dB。ADC核心面积为0.098 mm^(2)。A single-channel 8 bit 480 MS/s successive approximation register(SAR)analog-todigital converter(ADC)fabricated via 55 nm CMOS technology was presented. A dual-loop structure including an asynchronous clock loop and a data loop was exploited in the proposed high-speed SAR ADC. A dynamic comparator with reset switches was developed to shorten the reset time and improve the comparison accuracy. A reversed monotonic switching sequence approach was proposed to improve the working speed of ADC and mitigate comparator speed degradation due to decreasing input common-mode voltage. The measurement results show that the ADC achieves a FOMSof 147.3 dB,a SNDR of 42.7 dB and a SFDR of 50.53 dB under 100 MHz input signal,while consuming 6.9 mA current under 1.2 V power supply. The ADC core occupies 0.098 mm^(2) area.

关 键 词：SAR ADC 高速 反向单调切换逻辑 动态比较器 异步时钟 

分 类 号：TN43[电子电信—微电子学与固体电子学]