一种高电源电压抑制比的带隙基准电压源设计  

Design of a High Power Supply Rejection Ratio Bandgap Reference Voltage Source

作　　者：刘小妮 刘斌 张志浩[1,3] 章国豪 LIU Xiaoni;LIU Bin;ZHANG Zhihao;ZHANG Guohao(School of Information,Guangdong University of Technology,Guangzhou,510006,CHN;Guangzhou Suiyuan Microelectronics Technology Co.,Ltd,Guangzhou,510006,CHN;Synergy Innovation Institute of GDUT,Heyuan,Guangdong,517000,CHN)

机构地区：[1]广东工业大学信息工程学院,广州510006 [2]广州穗源微电子科技有限公司,广州510006 [3]河源广工大协同创新研究院,广东河源517000

出　　处：《固体电子学研究与进展》2021年第3期217-222,共6页Research & Progress of SSE

基　　金：广东省重点领域研发计划资助项目(2018B010115001);国家自然科学基金资助项目(61974035);广东省“珠江人才计划”本土创新科研团队资助项目(2017BT01X168)。

摘　　要：基于带隙基准原理,在自偏置共源共栅结构的基础上对传统带隙基准电路进行改进,通过在带隙核心电路中加入对应的NMOS管和PMOS管,构成一个三层叠共源共栅结构,显著提高了带隙基准源的电源电压抑制比。电路采用0.2μm的SOI工艺实现,实验室测试结果表明,该带隙基准电压源电路正常工作时输出基准电压为1.188 V,温度系数为5.4×10^(-6)/℃,启动时间约为2.2μs。Based on the principle of bandgap reference,the traditional bandgap reference circuit was improved on the basis of self-biased cascode structure in this paper. By adding the corresponding NMOS transistor and PMOS transistor to the bandgap core circuit,a three-stack cascode structure was formed,which significantly improved the power supply voltage suppression ratio of the bandgap reference source. The circuit is implemented using 0.2 μm SOI technology. Laboratory test results show that the output reference voltage of the bandgap reference voltage source circuit is 1.188 V,the temperature drift coefficient is 5.4×10^(-6)/℃,and the startup time is about 2.2 μs.

关 键 词：带隙基准 自偏置 三层叠共源共栅结构 电源电压抑制比 

分 类 号：TN432[电子电信—微电子学与固体电子学]