FPGA进位链64通道时间数字转换器设计  

64-Channel Time-to-Digital Converter Designed on Carry Chain of FPGA

作　　者：马毅超[1] 李煜 李贞杰[2] 李秋菊[2] 蒋俊国 MA Yi-chao;LI Yu;LI Zhen-jie;LI Qiu-ju;JIANG Jun-guo(Shaanxi University of Science and Technology,Xi’an 710021,China;Institute of High Energy Physics,Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]陕西科技大学,西安710021 [2]中国科学院高能物理研究所,北京100049

出　　处：《核电子学与探测技术》2020年第6期916-921,共6页Nuclear Electronics & Detection Technology

基　　金：国家自然科学基金(129-11705227)资助。

摘　　要：使用Xilink XC7K325TFBG676设计一种用于高能辐射光源(HEPS)APD探测器的64通道TDC。采用“粗计数”+“细测量”相结合的方法;通过Carry4构造64条抽头延时链,完成64通道的时间内插;采用两级触发器锁存结构降低亚稳态发生的概率;千兆以太网进行数据传输。实验结果表明:64通道TDC的最小时间分辨为49 ps,死时间为8 ns,时间测量精度为46.77 ps,微分非线性在[-0.1,0.12]lsb之间,积分非线性在[-0.1,0.31]lsb之间。The 64-channel time to digital converter is realized by Xilink XC7K325TFBG676 for High Energy Photon Source(HEPS)APD detector system.The method combining a coarse counter and a fine time interpolation based on FPGA carry-in delay line.The Carry4 module in the Kintex-7 series is used to construct 64 delay chains for each channel,Using two-stage flip-flop to reduce the probability of meta-stability and gigabit ethernet for data transmission.The test results show that 64-channel TDC minimum resolution was about 49 ps,dead time was 8 ns,time measurement accuracy(RMS)was about 46.77 ps,DNL was[-0.1,-0.12]lsb,INL was[-0.1,0.31]lsb.

关 键 词：同步辐射时间分辨 探测器 64通道 Carry4 TDC FPGA 

分 类 号：O572.21[理学—粒子物理与原子核物理] TN791[理学—物理]