基于FPGA的硬件抽象层设计  

Design of Hardware Abstraction Layer based on FPGA

作　　者：黄忠凡 代荣 孙健兴 李翔 HUANG Zhongfan;DAI Rong;SUN Jianxing;LI Xiang(Wuhan Zhongyuan Electronics Group Co.,Ltd.,Wuhan Hubei 430205,China)

机构地区：[1]武汉中原电子集团有限公司,湖北武汉430205

出　　处：《通信技术》2021年第7期1774-1779,共6页Communications Technology

摘　　要：基于共享内存交互的片上系统已经成为一种发展趋势。软件无线电的软件通信架构专门为此制定了一种硬件抽象层来屏蔽底层硬件差异性。基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)设计了该硬件抽象层,通过深入研究硬件抽象层工作原理总结出其设计要点,详细介绍了在ZYNQ FPGA中的实现方案,为他人设计硬件抽象层提供了参考。在实际环境中测试其性能,结果表明该硬件抽象层在实现了软件无线电架构移植灵活性,兼顾了波形处理的实时性。The system-on-chip based on shared memory interaction has become a development trend.The software communication architecture of software radio has specially formulated a hardware abstraction layer for this purpose to shield the differences in the underlying hardware.Based on Field Programmable Gate Array(FPGA),this paper designs the hardware abstraction layer.Through in-depth research on the working principle of the hardware abstraction layer,the main points of its design are summarized.It introduces the implementation scheme in ZYNQ FPGA in detail,and provides a reference for others to design the hardware abstraction layer.The performance was tested in an actual environment,and the results indicate that the hardware abstraction layer realizes the flexibility of software radio architecture transplantation while taking into account the real-time nature of waveform processing.

关 键 词：软件无线电 硬件抽象层 FPGA 共享内存 

分 类 号：TN924.3[电子电信—通信与信息系统]