HDB3编译码设计的FPGA实现  

Implementation of HDB3 Compiled Code on FPGA

作　　者：刘雪峰 张希 LIU Xuefeng;ZHANG Xi(Xi'an Traffi c Engineering Institute,Xi'an 710300,China;Xi'an Huanghe Photovoltaic Technology Co.,Ltd.,Xi'an 710048,China)

机构地区：[1]西安交通工程学院,陕西西安710300 [2]西安黄河光伏科技股份有限公司,陕西西安710048

出　　处：《数字通信世界》2021年第7期8-9,共2页Digital Communication World

摘　　要：设计了基于FPGA的HDB3编译码系统,由伪随机码产生模块、HDB3编码模块、HDB3译码模块、信号同步模块、显示模块五部分组成。用信号分析仪(ANT-5)测试了编译码系统,在一星期的测量周期内误码为零,测试结果验证了设计的正确性。The HDB3 coding and decoding system is designed on FPGA.It consists of five parts:pseudo-random code generation module,HDB3 coding module,HDB3 decoding module,signal synchronization module and display module.The codec system was tested with a signal analyzer(ANT-5).The bit error was 0 during the measurement period of one week.All results show that our designs are correct.

关 键 词：编译码 可编程逻辑器件 误码 

分 类 号：TN3[电子电信—物理电子学] TP31[自动化与计算机技术—计算机软件与理论]