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作 者:SHI Yong MA Zhong-Yuan CHEN Kun-Ji JIANG Xiao-Fan LI Wei HUANG Xin-Fan XU Ling XU Jun FENG Duan 史勇;马忠元;陈坤基;江小帆;李伟;黄信凡;徐岭;徐骏;冯端(National Laboratory of Solid State Microstructures,School of Electronic Science and Engineering,Nanjing University,Nanjing 210093)
出 处:《Chinese Physics Letters》2013年第7期198-201,共4页中国物理快报(英文版)
基 金:Supported by the National Basic Research Program of China under Grant No 2010CB934402;the National Natural Science Foundation of China under Grant Nos 61071008,10974091,and 60976001;the Fundamental Research Funds for the Central Universities under Grant Nos 1095021030,1116021004,and 1114021005.
摘 要:An nc-Si floating gate MOS structure is fabricated by thermal annealing of SiN_(x)/a-Si/SiO_(2).There are nc-Si dots isolated by a-Si due to partial crystallization.Conductance-voltage(G–V)measurements are performed to investigate the effect of multiple interface states including Si-sub/SiO_(2),a-Si related(as-deposited sample)and nc-Si(annealed sample)in a charge trapping/releasing process.Double conductance peaks located in the depletion and weak inversion regions are found in our study.For the as-deposited sample,the Si-sub/SiO_(2) related G–V peak with weak intensity shifts to the negative as test frequency increases.The a-Si related G–V peak with strong intensity shifts slightly with the increasing frequency.For the annealed sample,little change appears in the intensity and shift of Si-sub/SiO_(2) related G–V peaks.The position of a-Si/nc-Si related peak is independent of frequency,and its intensity is weaker compared to that of the as-deposited sample.It is also found that as the size of nc-Si becomes larger,the a-Si/nc-Si related peak shifts to the depletion region due to the size effect of nc-Si.
关 键 词:crystallization. process. annealed
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