5G NR小区搜索算法研究及FPGA实现  

Research on 5G NR cell search algorithm and FPGA implementation

作　　者：刘慧[1] 刘祖深[2] 许虎[2] 陈婷 Liu Hui;Liu Zushen;Xu Hu;Chen Ting(North China University,Taiyuan 030051,China;41st Research Institute,China Electronics Technology Group Corpora-tion,Bengbu 233006,China;Northern Information Control Research Institute Group Co.,Ltd.,Nanjing 211106,China)

机构地区：[1]中北大学,太原030051 [2]中国电子科技集团公司第四十一研究所,蚌埠233006 [3]北方信息控制研究院集团有限公司,南京211106

出　　处：《国外电子测量技术》2021年第6期152-158,共7页Foreign Electronic Measurement Technology

基　　金：中国电科集团专项创新基金项目(41Q1346)资助。

摘　　要：5G移动终端完成小区搜索流程后接入网络。针对传统数字信号处理(digital signal processing, DSP)串行模式内存消耗大的问题,提出了一种可用现场可编程门阵列(FPGA)实现的进行定时同步的方案。从工程实用的角度,主同步信号(primary synchronization signal, PSS)使用计算复杂度低且硬件实现难度较低的直接互相关算法。FPGA采用自顶层文件向下、多路并行模式、多级流水线结构的方法,提高了数据处理的效率,并经Xilinx vivado仿真平台测试,主要硬件资源占用率均在25%以内,满足工程要求,该方案己被应用到中国电科集团专项创新基金项目"5G专网多通道基站综测仪"的开发中。5 G mobile terminals access the network after completing the cell search process. Aiming at the problem of large memory consumption in serial mode of traditional digital signal processing(DSP), a timing synchronization scheme based on field programmable gate array(FPGA) is proposed. From the perspective of engineering practice, the primary synchronization signal(PSS) uses direct cross-correlation algorithm with low computational complexity and low hardware implementation difficulty. FPGA adopts the method of top-level file down, multi-channel parallel mode and multi-level pipeline structure, which improves the efficiency of data processing. Through the Xilinx vivado simulation platform test, the main hardware resource occupancy rate is less than 25%, which meets the engineering requirements. This scheme has been applied to the development of "5252 d multi-channel base station tester".

关 键 词：小区搜索 主同步信号 FPGA 5G NR 

分 类 号：TN929.5[电子电信—通信与信息系统]