0~21 GHz高精度宽带硅基数字衰减器设计  

Design of 0~21 GHz wideband silicon-based digital attenuator with high accuracy

作　　者：刘美杉 张为 郝东宁 LIU Mei-shan;ZHANG Wei;HAO Dong-ning(School of Microelectronics,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学微电子学院,天津300072

出　　处：《浙江大学学报（工学版）》2021年第7期1399-1406,共8页Journal of Zhejiang University：Engineering Science

摘　　要：针对射频前端收发系统中衰减结构宽带性能不稳定的问题,提出具有双重电容补偿的新型开关内嵌式衰减结构。该结构基于容性校正网络,在节约核心电路面积的同时通过调节零、极点对频率响应的影响,达到拓展衰减单元工作频带的目的,以满足跨频段、宽频域射频通信收发前端的设计需求.基于HHNEC 0.18μm SiGe BiCMOS工艺,采用新型电容补偿结构设计6位步进式数字衰减电路,该衰减器通过6位数控开关实现64种衰减状态,衰减步进0.5 dB,衰减范围0~31.5 dB.仿真结果表明,在0~21 GHz工作频带内衰减误差均方根小于0.23 dB,附加相移均方根小于4.38°,插入损耗最大为−11.05 dB,最小为−4 dB,中心频率处1 dB压缩点17.3 dBm,核心电路版图面积0.86 mm×0.2 mm.A new switch embedded attenuator structure based on capacitive correction network was presented,in order to solve the problem of unstable broadband performance in the RF front-end transceiver system.The capacitive correction network saving the core circuit area by adjusting the influence of the zero and pole to the frequency response,expanded the working band,which satisfied the cross-band,wide frequency domain RF design requirements for communication transceiver front end.A 6-bit digital step attenuator with the correction network based on HHNEC 0.18μm SiGe BiCMOS process was designed,the digital step attenuators had 6-bit digital control inputs with 64 attenuation states,the maximum attenuation of 31.5 dB and the least attenuation step of 0.5 dB.Simulation results show that in the bandwidth of 0~21 GHz,the 64-state root mean square(RMS)of attenuation error is less than 0.23 dB,the RMS of phase variation is less than 4.38°,the maximum insertion loss at 21 GHz is−11.05 dB,the minimum insertion loss is−4 dB,the 1 dB compression point at the center frequency is 17.3 dBm.The layout area of core circuit is 0.86 mm×0.2 mm.

关 键 词：数字步进式衰减器 相控阵雷达 高精度衰减 低附加相移 超宽带 体悬浮技术 

分 类 号：TN433[电子电信—微电子学与固体电子学]