SiC MOSFET栅源回路参数的串联扰动研究  

Research on Series Disturbance of SiC MOSFET Gate-source Loop Parameters

作　　者：张宇 李先允[1] 王书征[1] 唐昕杰 袁宇 卢乙 ZHANG Yu;LI Xianyun;WANG Shuzheng;TANG Xinjie;YUAN Yu;LU Yi(School of Electric Power Engineering,Nanjing Institute of Technology,Nanjing 211167,Jiangsu,China)

机构地区：[1]南京工程学院电力工程学院,江苏南京211167

出　　处：《电气传动》2021年第16期33-38,共6页Electric Drive

基　　金：江苏省重点研发计划项目(BE2018130);江苏省普通高校研究生科研创新计划项目(No.SJCX18_0575)。

摘　　要：为了使SiCMOSFET工程运用时避免串联扰动的威胁,研究栅源回路参数对串联扰动的影响是很有必要的。研究通过对栅源回路参数的调控,将串联扰动现象分为正压尖峰与负压尖峰两部分进行分析,确定影响串扰电压尖峰的参数,为驱动回路参数设计提供方向性意见。首先建立拓扑简化模型,理论分析影响电压尖峰的栅源回路参数,随后搭建实验平台进行电压尖峰观测以及对理论分析进行实验验证,最后对实验波形进行分析。实验表明,当驱动电阻为0~20Ω、驱动杂散电感为0~300 nH、栅极电容为0~10 nF时,串联扰动随着桥臂自身驱动电阻、驱动杂散电感的增大而增大、随着栅极电容的增大而减小。此外,负载阻抗会影响负压尖峰,尖峰震荡同样会影响器件正常工作。In order to avoid the threat of series disturbance during the engineering application of SiC MOSFET,it is necessary to study the influence of driving circuit parameters on the series disturbance.Based on the adjustment of the gate-source loop parameters,the series disturbance phenomenon was divided into two parts in this study:positive pressure spike and negative pressure spike.First,a simplified topology model was established,and the gate-source loop parameters that affect voltage spikes were theoretically analyzed.Then an experimental platform was set up to observe the voltage spikes and verify the theoretical analysis.Finally,the experimental waveforms were analyzed.Experiments show that when the driving resistance is 0~20Ω,the driving stray inductance is 0~300 nH,and the gate capacitance is 0~10 nF,the series disturbance increases with the increase of the driving resistance and driving stray inductance of the bridge arm,but it decreases as the gate capacitance increases.In addition,negative pressure spikes will be affected by load impedance,normal operation of the device will also be affected by the spike oscillation.

关 键 词：碳化硅MOSFET 栅源回路 串联扰动 电压尖峰 

分 类 号：TM131.2[电气工程—电工理论与新技术]