基于JESD204B协议高速并行8bit/10bit解码电路设计  

Design of High Speed Parallel 8 bit/10 bit Decoding Circuit Based on JESD204B Protocol

作　　者：万书芹[1] 陈婷婷 陶建中[1,2] 蒋颖丹[1] 朱夏冰 Wan Shuqin;Chen Tingting;Tao Jianzhong;Jiang Yingdan;Zhu Xiabing(The 58lh Research Institute,CETC,Wuxi 214035,China;College of loT Enginnering,Jiangnan University,Wuxi 214122,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035 [2]江南大学物联网工程学院,江苏无锡214122

出　　处：《半导体技术》2021年第8期604-610,622,共8页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61704161)。

摘　　要：提出了一种高速低延时8 bit/10 bit解码电路结构,采用四路并行通道同时处理输入数据,每一路具有K码检测、输入数据查错功能,能够在输入四路10 bit数据后的一个时钟周期内正确完成解码。所设计的解码电路通过搭建的通用验证方法学系统完成系统级功能验证,并基于65 nm工艺库进行综合、布局和布线,解码电路的面积为1 449μm^(2)。后仿真结果显示,解码电路的最高工作频率达415 MHz,四路可支持最高16.6 Gibit/s的串行数据传输速率,满足JESD204B协议标准推荐的最高传输速率12.5 Gibit/s的要求。将该解码电路用于支持JESD204B协议的高速数模转换器电路中,经测试,其传输速率最高达10.5 Gibit/s。A high speed and low latency 8 bit/10 bit decoding circuit structure was proposed, which adopted four parallel channels to process input data at the same time.Each channel has the functions of K-code detection and input error checking, and input 10 bit data of the four channels can be correctly decoded within one clock cycle.The designed decoding circuit was verified by the universal verification methodology system which built for the system-level functional verification.Based on 65 nm process library synthesis, layout and wiring, the area of the decoding circuit is 1 449 μm^(2).The post simulation results show that the maximum working frequency of the decoding circuit is up to 415 MHz, and the four channels can support 16.6 Gibit/s serial data transmission rate, which meets the requirement of the JESD204 B protocol standard for the highest transmission rate of 12.5 Gibit/s.It is applied in the high speed digital-to-analog converter circuit to support JESD204 B protocol, and the tested transmission rate is up to 10.5 Gibit/s.

关 键 词：8 bit/10 bit 并行解码 低延时 JESD204B协议 串行解串器 

分 类 号：TN47[电子电信—微电子学与固体电子学]