基于VerilogA模型的PLL环路带宽设计方法  

Design Method of PLL Loop Bandwidth Based on VerilogA Model

作　　者：吴浩[1] 季渊[1,2] 郑志杰 张引 穆廷洲 Wu Hao

机构地区：[1]上海大学微电子研究与开发中心,上海200072 [2]上海大学机电工程与自动化学院,上海200072

出　　处：《工业控制计算机》2021年第8期143-145,164,共4页Industrial Control Computer

基　　金：国家自然科学基金资助(61774101)

摘　　要：先根据系统要求,结合Matlab计算出LPF的RC参数。采用verilogA建模,对锁相环模型输出端波形做功率谱密度分析并计算相位噪声。用噪声和抖动语句为VerilogA模型各模块添加与实际电路一致的相位噪声,用模型代替实际锁相环电路,通过调节预设环路带宽,得到最小的VCO输出端相位噪声并得到最佳的环路带宽。使用的实际电路采用SMIC11MMRF_1233工艺,电路级锁相环已成功流片,实验结果表明VerilogA模型相比于电路级锁相环极大的缩短了仿真时间。In this paper,according to the system requirements,the RC parameters of LPF are calculated by MATLAB.The output waveform of PLL VerilogA model is used to analyse power spectral density and the phase noise is calculated,this paper uses noise and jitter statements to add the phase noise which consistent with the practical circuit for each module of VerilogA model,and use the model to replace the practical phase-locked loop circuit.By adjusting the loop bandwidth,can get the minimum VCO output phase noise and get the best loop bandwidth.The practical circuit used in this paper is smic11mmrf_1233.The experiment results show that the VerilogA model can greatly shorten the simulation time compared with the circuit level PLL.

关 键 词：VerilogA 锁相环 环路带宽 相位噪声 

分 类 号：TN911.8[电子电信—通信与信息系统]