基于FPGA的卷积神经网络加速器设计  

Design of Accelerator for Convolution Neutral Network Based on FPGA

作　　者：胡俊杰 陈仕川[1,2] HU Jun-jie;CHEN Shi-chuan(Science and Technology on Communication Information Security Control Laboratory,Jiaxing Zhejiang 314033,China;No.36 Research Institute of CETC,Jiaxing Zhejiang 314033,China)

机构地区：[1]通信信息控制和安全技术重点实验室,浙江嘉兴314033 [2]中国电子科技集团公司第三十六研究所,浙江嘉兴314033

出　　处：《通信对抗》2020年第3期28-33,共6页Communication Countermeasures

摘　　要：基于深度学习的分类方法广泛应用于图像/视频分类、场景分析检测等场合,现已被引入信号处理领域。根据卷积神经网络的特点,提出一种基于单片FPGA的卷积神经网络加速器设计方案,通过深度流水和并行化设计,充分发挥FPGA并行运算效能,通过分时复用计算资源来完成整个网络的加速计算过程。The classification method base on deep learning technology has been widely used in image/video classify,recentlyit has been introduce to signal processing area.According to the characteristics of the Convolution Neural Network(CNN),a acceleration method for Convolution Neural Network(CNN)which is realized in single FPGA is proposed,by using the deep—pipeling and parallelize architecture,it exert the calculation capability of the FPGA sufficiently,and it will finish the whole calculation process of the entire network by TDM technology.

关 键 词：卷积神经网络(CNN) 可编程逻辑器件(FPGA) 加速器 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程]