基于FPGA的高阶组合结构FIR数字滤波器设计  

Design of high order mixed architecture FIR digital filter based on FPGA

作　　者：蒋林 葛中芹[1] 杨旭 姜乃卓[1] 庄建军[1] JIANG Lin;GE Zhongqin;YANG Xu;JIANG Naizhuo;ZHUANG Jianjun(School of Electronics Science and Engineering,Nanjing University,Nanjing 210023,China)

机构地区：[1]南京大学电子科学与工程学院,江苏南京210023

出　　处：《实验室科学》2021年第3期72-77,共6页Laboratory Science

基　　金：2017年教育部第二批产学合作协同育人项目(项目编号:201702007014);南京大学“十三五”实验教学改革研究重点课题(项目编号:SY201708,SY201814,SY201815)。

摘　　要：传统数字信号处理实验大都是基于Matlab软件的滤波器设计和仿真,为满足工程上实时性的要求,设计了一个以FPGA处理器为核心的FIR数字滤波器实验。为了兼顾运算速度和硬件资源消耗,采用8路并行乘加运算的组合结构,在FPGA平台上实现了511阶的高阶FIR带通滤波器。通过实验进一步研究了A/D采样位数不同时,滤波器系数量化位数对滤波性能和频率响应曲线精度的影响。实验结果表明,当输入模拟信号分别使用8bit和12bit采样时,滤波器系数量化位数分别取11位和13位,得到的幅频响应精度最高,硬件资源消耗最少。The traditional digital signal processing experiments are mostly based on Matlab software for filter design and simulation.In order to meet the real-time filtering requirements of engineering applications,this paper proposes a FIR digital filtering experiment based on FPGA.In order to give consideration to both computing speed and hardware resource consumption,a combination of 8 parallel multiply-accumulate operations is adopted to implement a 511-order high order FIR bandpass filter on FPGA.Furthermore,the paper also studies the influence of the quantized bits of filter coefficients on the filtering performance and the accuracy of the frequency response when the A/D sampling bits are different.The experimental results show that when the input analog signals are sampled by 8 bits and 12 bits,the quantized bits of the filter coefficients should be taken as 11 bits and 13 bits respectively in order to obtain the highest amplitude frequency response accuracy and the minimum hardware resource consumption.

关 键 词：FPGA处理器 FIR滤波器 系数量化 幅频特性 

分 类 号：TN911.72[电子电信—通信与信息系统]