高吞吐率低时延图像DCT处理器设计  

Design of high throughput rate low latency image DCT processor

作　　者：刘思军 秦明伟[1] 刘多强 Liu Sijun;Qin Mingwei;Liu Duoqiang(School of Information Engineering,Southwest University of Science and Technology,Mianyang 621010,China;China Helicopter Design and Research Institute,Jingdezhen 333000,China)

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010 [2]中国直升机设计研究所,江西景德镇333000

出　　处：《电子技术应用》2021年第9期69-74,共6页Application of Electronic Technique

基　　金：国家重大科学仪器设备开发基金资助项目(2016YFF0104006);西南科技大学研究生创新基金项目(20ycx0063)。

摘　　要：针对高分辨率、高帧率图像实时压缩问题,设计了一种应用于高速图像JPEG压缩编码系统的离散余弦变换(DCT)处理器。设计的DCT处理器基于Virtex-7系列FPGA,充分利用并行和流水线处理技术,采用基于蝶形流图结构的行列分解算法,实现了快速二维离散余弦变换(2D-DCT)。为了提高数据吞吐率,设计了双核DCT处理单元,可同时处理16个像素,从整体上提高处理速度和降低时延。板级测试表明,高速图像DCT处理器数据计算结果正确,在200 MHz系统时钟下,吞吐率高达3 GB/s,此时平均每帧图像处理时间不超过10 ms,实现了高速图像的实时处理。Aiming at the high-resolution and high-frame rate image real-time compression problem,a discrete cosine transform processor for high-speed image JPEG compression coding system was designed.The designed discrete cosine transform(DCT)processor is based on the Virtex-7 series FPGA,which makes full use of parallel and pipeline processing technology,and implements a fast two-dimensional discrete cosine transform(2D-DCT)by using a matrix-like decomposition algorithm based on the butterfly flow graph structure.In order to improve the data throughput rate,a dual-core DCT unit is designed to process 16 pixels at the same time,which improves the processing speed and reduces the delay as a whole.The board test shows that the calculation results of high-speed image DCT processor are correct.Under the 200 MHz system clock,the throughput rate is up to 3 GB/s,and the average image processing time per frame is no more than 10 ms,realizing the real-time processing of high-speed images.

关 键 词：图像压缩 DCT FPGA 并行流水结构 高吞吐率 低时延 

分 类 号：TN911[电子电信—通信与信息系统] TP335[电子电信—信息与通信工程]