基于FPGA的多通道多电平高压信号发生器  

Multi⁃channel and multi⁃level high voltage signal generator based on FPGA

作　　者：周家辉[1] 刘一清[1] ZHOU Jiahui;LIU Yiqing(School of Communication and Electronic Engineering,East China Normal University,Shanghai 200241,China)

机构地区：[1]华东师范大学通信与电子工程学院,上海200241

出　　处：《电子设计工程》2021年第19期174-178,共5页Electronic Design Engineering

摘　　要：针对MEMS数字微镜驱动波形电压高、电平多、通道多的难点,文中设计了一种基于FPGA的多通道多电平高压信号发生器。硬件电路分为核心控制电路与功率驱动电路两大部分。核心控制电路以Xilinx Artix-7 FPGA与ARM Cortex-M7内核STM32微处理器为核心,利用FPGA产生时序精密、程控可调的多通道PWM波,控制功率驱动电路MOS管的开关,利用微处理器实现用户交互接口控制。功率驱动电路采用级联半桥拓扑产生多电平高压信号,同时利用“悬浮式”电路结构,降低了多电平驱动信号产生电路的复杂度与对电路元件耐压值的要求。设计了硬件电路,同时基于Qt设计了PC端人机交互界面,实现了新型数字微镜器件64路8电平60 V高电压复杂驱动波形的信号发生器。In view of the difficulties of high voltage,multi⁃level and multi⁃channel driving waveform of MEMS digital micromirror,a multi⁃channel multi⁃level high⁃voltage signal generator based on FPGA is designed in this paper.The hardware circuit is divided into two parts:the core control circuit and the power driving circuit.The core control circuit uses Xilinx Artix-7 FPGA and STM32 microprocessor with ARM Cortex-M7 core.FPGA is used to generate program controlled multi⁃channel PWM wave with precise timing and control the MOSFET switch of the power driving circuit.Microprocessor is used to realize the user interface.The cascaded half bridge topology is used in the power drive circuit to generate multi⁃level high⁃voltage signals.At the same time,the‘levitated’circuit structure is used to reduce the complexity of the multi⁃level drive signal generation circuit and the requirement of the circuit component durable voltage value.The hardware circuit is designed,the PC human⁃computer interface is designed based on Qt,and the 64 channel 8-level 60 V high⁃voltage complex driving waveform signal generator of the new digital micromirror is realized.

关 键 词：电子技术 级联半桥 FPGA 多电平信号 

分 类 号：TN98[电子电信—信息与通信工程]