一种适用于TSN端系统的DMA控制器的设计与仿真分析  

Design and Simulation of a Direct Memory Access Controller for End Station in TSN

作　　者：杜婧 乔庐峰 陈庆华 王雷淘 DU Jing;QIAO Lufeng;CHEN Qinghua;WANG Leitao(Army Engineering University of PLA,Nanjing Jiangsu 210001,China)

机构地区：[1]陆军工程大学,江苏南京210001

出　　处：《通信技术》2021年第9期2257-2263,共7页Communications Technology

摘　　要：根据时间敏感网络(Time Sensitive Network,TSN)对端系统的设计需求,设计了一种支持多个逻辑队列且缓冲区共享的直接存储访问(Direct Memory Access,DMA)控制器。DMA控制器内部收发方向上各支持8个逻辑队列,多个逻辑队列共享位于内存中的缓存空间,可对不同类型的数据帧提供差异化的收发调度和处理。DMA控制器采用基于指针的收发逻辑队列结构和复杂的缓冲区描述符,可以有效降低处理器负荷,提高总线吞吐率。整个设计在Xilinx ZYNQ7035的开发板上进行了仿真分析和功能验证。To meet requirements of end station in TSN(Time Sensitive Network),a DMAC(Direct Memory Access Controller)which supports multiple logical queues and shared buffers is presented.DMAC supports 8 logical queues in receiving and sending direction.All the logical queues share the buffers located in the memory,which can provide differentiated dispatch and processing for different types of data frames.DMAC adopts pointer based logical queues structure and complex buffer descriptor,which can reduce the load of the processor and improve the bus throughput effectively.The whole design is simulated and verified on the Xilinx Zynq7035 FPGA.

关 键 词：时间敏感网络 直接存储器访问 AXI总线 描述符 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TP393.1[自动化与计算机技术—计算机科学与技术]