A fully integrated CMOS 60-GHz transceiver for IEEE802.11ad applications  

作　　者：ZHANG Lei LUO Jun ZHU Wei ZHANG Li WANG Yan YU Zhiping 

机构地区：[1]Institute of Microelectronics,Tsinghua University,Beijing 100084,China

出　　处：《Journal of Communications and Information Networks》2016年第2期45-61,共17页通信与信息网络学报（英文）

基　　金：supported by The National High Technology Research and Development Program of China(No.2011AA010202,No.2015AA01A704);The National Natural Science Foundation of China(No.61101001,No.61204026,No.61331003);The Tsinghua University Initiative Scientific Research Program.

摘　　要：A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology.The reported transceiver monolithically integrates a receiver,transmitter,PLL(Phase-Locked Loop)synthesizer,and LO(Local Oscillator)path based on a sliding-IF architecture.The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel,with an EVM(Error Vector Magnitude)of lower than−20 dB.The receiver path achieves a configurable conversion gain of 36~64 dB and a noise figure of 7.1 dB over 57~64 GHz,while consuming only 177 mW of power.The transmitter achieves a conversion gain of roughly 26 dB,with an output P1dB of 8 dBm and a saturated output power of over 10 dBm,consuming 252 mW of power from a 1.2-V supply.The LO path is composed of a 24-GHz PLL,doubler,and a divider chain,as well as an LO distribution network.In closed-loop operation mode,the PLL exhibits an integrated phase error of 3.3ºrms(from 100 kHz to 100 MHz)over prescribed frequency bands,and a total power dissipation of only 26 mW.All measured results are rigorously loyal to the simulation.

关 键 词：60 GHz TRANSCEIVER CMOS sliding IF circuit/EM co-design LNA PA PGA 

分 类 号：TN7[电子电信—电路与系统]