任意占空比数字信号位同步时钟盲提取的数字实现  

Digital Realization of Blind Extraction for Bit Synchronized Clock of Digital Signal with Any Duty Cycle

作　　者：赵仕良[1] 谷婧 张婕 汪文蝶 ZHAO Shiliang;GU Jing;ZHANG Jie;WANG Wendie(College of Physics and Electronic Engineering,Sichuan Normal University,Chengdu 610101)

机构地区：[1]四川师范大学物理与电子工程学院,成都610101

出　　处：《电子科技大学学报》2021年第5期710-719,共10页Journal of University of Electronic Science and Technology of China

摘　　要：该文用FPGA和DSP设计的双核数字系统结合软件算法完成了任意占空比数字信号的自动识别,实现了较宽范围的位同步时钟盲提取。同时根据双向打点原理,详细分析了盲提取位同步时钟频率产生误差的原因,并总结出双向打点盲提取频率相对误差和最大相对误差的公式。该公式对所有双向打点系统具有理论指导和工程实践意义。通过测试,采用150 MHz的打点时钟,对于12 Kbps以下的单极性非归零数字信号,可以很好地实现盲同步的频率跟随性。实验数据表明:对于相同速率的单极性非归零码(NRZ)和占空比为D的单极性归零码(RZ),RZ的盲提取频率相对误差是NRZ的1/(D,1−D)_(min)倍。实验结论证明该文建立的盲提取频率相对误差公式是正确的。This paper proposes a dual-core digital system which is designed by using field programmable gate array(FPGA)and digital signal processing(DSP).The system applies software algorithm to realize automatic identification of digital signal with arbitrary duty cycle and wide range of blind extraction of synchronous clock.At the same time,according to the principle of two-way dotting,the reason causing the error of blind extraction bit synchronous clock frequency is analyzed in detail,and the formulas of relative error and maximum relative error of blind extraction frequency of two-way dot are summarized.The formulas have theoretical guidance and practical significance for all two-way dot systems.Through the test,by using 150MHz clock,frequency tracking in blind synchronization can be realized for the single-polarity not-return-to-zero digital signal below 12Kbps.The experimental data show that for the same rate of unipolar not-return-to-zero code(NRZ)and unipolar return-to-zero code(RZ)with duty cycle D,the relative error of blind extraction frequency of RZ is 1/(D,1−D)min times that of NRZ.The experimental results show the validity of the relative error formulas of blind extraction frequency.

关 键 词：盲提取 位同步时钟 占空比 数字实现 位同步时钟频率最大相对误差 

分 类 号：TN911.72[电子电信—通信与信息系统]