10位低功耗逐次逼近型模数转换器的设计  

Design of 10-bit Low-power Successive Approximation Analog-to-digital Converter

作　　者：杨臻 YANG Zhen(College of Physics and Information Engineering,Fuzhou University)

机构地区：[1]福州大学物理与信息工程学院

出　　处：《中国集成电路》2021年第10期18-21,26,共5页China lntegrated Circuit

摘　　要：本文提出了一种10位低功耗逐次逼近型(Successive Approximation Register,SAR)模数转换器。电路采用分段式电荷型数模转换器和全动态比较器,使得本设计在同等采样速率下具有更高分辨率及更低功耗,同时具有良好的线性度和较广的输入范围。本设计采用SMIC 0.18μm CMOS工艺,电源电压为1.2V,采样速率为6MS/s。仿真结果表明,ADC的SFDR为81.5dB,SNDR为59.9dB,其能达到9.65bit分辨率,且功耗仅为0.091mW。In this paper,a 10-bit low-power successive approximation(Successive Approximation Register,SAR)analog-to-digital converter is proposed.The circuit combines a segmented charge type digital-to-analog converter and a full-dynamic comparator to achieve higher resolution and lower power consumption at the same sampling rate,having good linearity and a wider input range as well.This design uses SMIC 0.18μm CMOS process,with supply voltage of 1.2V and sampling rate of 6 MS/s.The simulation results show that the ADC achieves an SFDR of 81.5dB,SNDR of 59.9dB,resolution of 9.65bit,and consumes only 0.091mW.

关 键 词：SAR ADC 全动态比较器 分段式数模转换器 低功耗 

分 类 号：TN792[电子电信—电路与系统]