Analysis on Three-Dimensional Gate Edge Roughness of Gate-All-Around Devices  

作　　者：SUN Shuang LI Ming ZHANG Baotong LI Xiaokang CAI Qifeng LI Haixia BI Ran XU Xiaoyan HUANG Ru 

机构地区：[1]Department of Micro-Nanoelectronics,Peking University,Beijing 100871,China [2]Beijing Laboratory of Future IC Technology and Science,Peking University,Beijing 100871,China

出　　处：《Chinese Journal of Electronics》2021年第5期861-865,共5页电子学报（英文版）

基　　金：the National Key Research and Development Plan(No.2016YFA0200504);the National Natural Science Foundation of China(No.61927901)。

摘　　要：As the physical size of metal-oxide-semiconductor field effect transistor approaches the end of scaling down,the effect of process-induced variations such as gate edge roughness on device performance cannot be neglected.For gate-all-around devices,the threedimensional gate profiles make the evaluation of gate edge roughness different and more complicated than that in planar metal-oxide-semiconductor field effect transistors.In this work,an evaluation algorithm was proposed to model the three-dimensional gate edge roughness in a real gate-all-around device.The results show that the typical trapezoidal gate is more likely to suffer from gate edge roughness effect than the ideal rectangular gate.The effect of the size of the gate and the correlation coefficient of the edges on the effective channel length variation was also studied.

关 键 词：Gate-all-around devices Trapezoidal gate profile Gate edge roughness Effective channel length Threshold voltage variation 

分 类 号：TN386[电子电信—物理电子学]