图计算加速器中稀疏向量比较单元的设计与实现  

DESIGN AND IMPLEMENTATION OF SPARSE VECTOR COMPARISON UNIT IN GRAPH PROCESSING ACCELERATOR

作　　者：田璞 蒋林 邓军勇 赵一迪 刘新闯 樊萌 Tian Pu;Jiang Lin;Deng Junyong;Zhao Yidi;Liu Xinchuang;Fan Meng(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,Shaanxi,China;Integrated Circuit Design Laboratory,Xi’an University of Science and Technology,Xi’an 710054,Shaanxi,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安科技大学集成电路设计实验室,陕西西安710054

出　　处：《计算机应用与软件》2021年第10期61-66,130,共7页Computer Applications and Software

基　　金：国家自然科学基金项目(61834005,61772417,61802304,61602377,61874087);陕西省科技统筹创新工程项目(2016KTZDGY02-04-02);陕西省重点研发计划项目(2017GY-060);陕西国际科技合作计划项目(2018KW-006)。

摘　　要：绝大多数图计算应用都可以映射为稀疏矩阵和向量运算,稀疏向量的比较运算是稀疏矩阵向量运算的计算瓶颈,为解决图计算加速器中稀疏矩阵列向量比较问题,设计一种稀疏向量比较运算电路,主要包括64个比较运算电路和一个共享存储单元。基于Verilog HDL语言完成电路设计,以SNAP(Stanford Network Analysis Project)上的Flickr数据集为例,在ModelSim SE-6410.1c完成验证工作,采用Xilinx公司的ISE开发环境对硬件电路进行综合,实验结果表明,该电路的工作频率可以达到264 MHz。Most graph processing applications can be mapped to sparse matrices and vector operations.Sparse vector comparison operations are computational bottlenecks for sparse matrix vector operations.To solve the problem of sparse matrix column vector comparison in graph computation accelerators,we propose a sparse vector comparison operation circuit.This circuit consisted of 64 compare operation circuits and a shared memory unit.The circuit design was completed based on the Verilog HDL language.Take the Flickr dataset on the SNAP(Stanford Network Analysis Project)as an example to complete the verification work in ModelSim SE-6410.1c.The hardware circuit was integrated by Xilinx s ISE development environment.The experimental results show that the circuit can work at 264 MHz.

关 键 词：图计算 稀疏列向量 比较运算 SNAP 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]