低杂散、低相噪的电荷泵锁相环设计  

Design of Low-spur and Low-phase-noise CPPLL

作　　者：蒲明臻 赵宏亮[1] 鲜卓霖 廖奎旭 孙宝琛 李旺 PU Mingzhen;ZHAO Hongliang;XIAN Zhuolin;LIAO Kuixu;SUN Baochen;LI Wang(Liaoning University,School of Physics,Shefiyang,110000,CHN;Chengdu CORPRO Technology CO.,LTD.Chengdu,610000,CHN)

机构地区：[1]辽宁大学物理学院,沈阳110000 [2]成都振芯科技股份有限公司,成都610000

出　　处：《固体电子学研究与进展》2021年第4期285-290,共6页Research & Progress of SSE

摘　　要：基于华虹0.18μm SiGe BiCMOS工艺设计了一款低杂散、低相噪的电荷泵锁相环频率合成器芯片,其最高工作频率为400 MHz,射频输入频率范围为5~400 MHz,输入参考信号频率范围为20~300 MHz。本设计通过外接低通滤波器、压控振荡器,可实现完整的锁相环,如果把R/N分频都设置为"1",芯片也可以单独当作电荷泵和鉴频鉴相器。芯片测试结果为:归一化相位噪声基底(噪声优值)为-228 dBc/Hz,电流源与电流沉失配小于2%,参考杂散为-107.6 dBc,带内噪声为-115 dBc/Hz@10 kHz。Based on the 0.18 μm SiGe BiCMOS process,a low-noise and low-noise charge pump phase locked loop(CPPLL)frequency combination chip was designed. The maximum working frequency of the chip is 400 MHz,and the frequency range of RF input frequency is 5~ 400 MHz,and the frequency range of the input reference signal is 20~ 300 MHz. This chip can realize the complete PLL through the external low-pass filter(LPF)and voltage control oscillator(VCO),and if the R/N frequency divider is set to be“1”,it can also be used as the charge pump and the phase frequency detector. Test results of the chip show that the return of the phase noise base(figure of merit)is-228 dBc/Hz,the mismatch of current source and current sink are less than 2%,the reference spur is-107.6 dBc,the noise in the band is-115 dBc/Hz@10 kHz.

关 键 词：锁相环 电荷泵 低相噪 低杂散 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN433