一种低功耗时钟树的设计和优化方法  

A low-power clock tree design and optimization method

作　　者：朱佳琪 陈岚[1,3] 王海永 ZHU Jiaqi;CHEN Lan;WANG Haiyong(Institute of Microelectronics of China Academy of Science,Beijing 100029,China;University of Chinese Academy of Science,Beijing 100049,China;Beijing Key Laboratory of 3D and Nano Integrated Circuit Design Automation Technology,Beijing 100029,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049 [3]三维及纳米集成电路设计自动化技术北京市重点实验室,北京100029

出　　处：《微电子学与计算机》2021年第10期85-90,共6页Microelectronics & Computer

基　　金：北京市科技计划国产EDA工具产业链应用推广示范平台项目(Z201100004220005)。

摘　　要：本文研究纳米工艺下低功耗时钟树的设计和优化方法.以时钟信号的转换时间和负载电容作为实现时钟树低功耗的两个设计变量,基于时钟网络的寄生电阻-电容模型,分析出金属布线宽度减小、间距变大可以降低时钟树功耗,但是,该方法会对时钟树的时序产生影响.于是,本文提出一种以低功耗和低时序违例为联合约束条件的时钟树设计和优化方法,并给出了低功耗时钟树综合设计流程.实验证明,与一般经验设计相比,本文提出的时钟树设计和优化方法在典型情况下可以降低时钟网络的动态功耗10.3%,总的时序违例降低7.07%.This paper studies the design and optimization method of low-power clock tree under nanotechnology.Based on the two design variables,the transition time and the load capacitance of the clock signal,and the parasitic resistance-capacitance model of the clock networks,the paper shows that,with the reduced width or enlarged space of the metal wire,the power consumption of the clock tree can be reduced,meanwhile,the timing of the clock tree can also be violated..Therefore,this paper proposes one joint optimization method of clock tree with low-power and low timing violations,and gives a low power clock tree synthesis design flow.The results show that,compared with the general rules of experience method,the optimization method proposed in this paper can reduce the dynamic power consumption of the clock network by 10.3%and reduce the total timing violation by 7.07%under typical condition.

关 键 词：动态功耗 负载电容 转换时间 时钟布线 设计流程 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN432