基于AD9954的DDS激励双PLL宽频带时钟合成模块的实现  

Implementation of DDS Driven Dual PLL Broadband Clock Synthesizer Based on AD9954

作　　者：廖成宇 李璐 代锴垒 谢豪 寸怡鹏 Liao Chengyu;Li Lu;Dai Kailei;Xie Hao;Cun Yipeng(Nuclear Power Institute of China National Key Laboratory of Reactor System Design Technology,Chengdu,610213)

机构地区：[1]中国核动力研究设计院核反应堆系统设计技术国家级重点实验室,四川成都610213

出　　处：《中国仪器仪表》2021年第8期50-53,共4页China Instrumentation

摘　　要：利用直接数字频率合成法(DDS)和锁相频率合成法(PLL)相组合的时钟信号合成方法,来完成宽频带、低抖动时钟信号输出模块的开发。其中,采用FPGA完成对DDS芯片、PLL芯片和继电器相关控制引脚的信号控制,实现时钟信号的产生和选频分段输出。测试结果表明,模块输出的时钟信号满足预期的开发要求。The clock signal synthesis method of direct digital frequency synthesis(DDS) and phaselocked frequency synthesis(PLL) is used to develop the clock signal output module of broadband and low jitter. Among them, FPGA is used to complete the signal control of DDS chip, PLL chip and relay related control pin, and the clock signal generation and frequency selection output are realized. The test results show that the clock signal output by the module meets the expected development index.

关 键 词：直接数字频率合成 锁相环 时钟合成 FPGA 

分 类 号：TN74[电子电信—电路与系统]