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作 者:徐砚天 黄晓敏 李浩明 王志宇[1] 郁发新[1] XU Yan-tian;HUANG Xiao-min;LI Hao-ming;WANG Zhi-yu;YU Fa-xin(College of Aeronautics and Astronautics,Zhejiang University,Hangzhou 310027,China;Hangzhou Chengxin Technology Limited company,Hangzhou 310030,China)
机构地区:[1]浙江大学航空航天学院,浙江杭州310027 [2]杭州城芯科技有限公司,浙江杭州310030
出 处:《浙江大学学报(工学版)》2021年第9期1788-1794,共7页Journal of Zhejiang University:Engineering Science
摘 要:为了在多通道射频(RF)通信系统中,实现多个收发器芯片或单个收发器芯片上的锁相环(PLL)相位同步,提出小数分频PLL输出信号相位同步算法.设计相位累加采样点数选取算法,算法选取的采样点数用于累加参考时钟欠采样的PLL输出信号与数控振荡器(NCO)产生的参考信号经三角运算的结果,以消除高次谐波分量,并有效降低相位差计算结果的误差.根据相位差的计算结果反馈调节PLL内delta-sigma调制器(DSM)输入的小数分频比,线性调整PLL输出信号的相位,实现多个PLL输出信号相位与参考信号相位同步.通过仿真验证算法的正确性,且最终相位同步后的相位误差为0.35°,完成同步所需的时间为210 ms.An algorithm of fractional frequency phase locked loop(PLL)output signal phase synchronization was proposed,in order to realize the phase synchronization of PLL on multiple transceiver chips or a single transceiver chip in a multi-channel radio frequency(RF)communication system.A selection algorithm of sampling points for phase accumulation was designed.The sampling points selected by the algorithm were used to accumulate the triangulation results of PLL’s output signal under sampled by reference clock and reference signal generated by NC oscillator(NCO),so as to eliminate the high-order harmonic component and reduce the error of the phase difference calculation result effectively.According to the size of the phase difference,the fractional frequency ratio of the input of delta-sigma modulator(DSM)in PLL was adjusted by feedback,so that the phase of PLL output signal was adjusted linearly,and the phase synchronization of multiple PLL output signals with reference signal was realized.The correctness of the algorithm is verified by simulation,and the phase error is 0.35°after the final phase synchronization,and the time required to complete the synchronization is 210 ms.
关 键 词:小数分频锁相环 相位同步 多芯片同步 多通道射频通信 相位差计算
分 类 号:TN402[电子电信—微电子学与固体电子学]
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