多核SoC中外部存储器并行访存控制器设计  

Design of off-chip memory parallel access controller in multi-core SoC

作　　者：王泽中 王春华[1] 王正茂 张多利[1,2] WANG Zezhong;WANG Chunhua;WANG Zhengmao;ZHANG Duoli(School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230601, China;IC Design Web-cooperation Research Center of Ministry of Education, Hefei 230601, China)

机构地区：[1]合肥工业大学电子科学与应用物理学院,安徽合肥230601 [2]教育部IC设计网上合作研究中心,安徽合肥230601

出　　处：《合肥工业大学学报（自然科学版）》2021年第10期1353-1358,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61874156)。

摘　　要：当前外部存储器的带宽不断提高,文章针对多核片上系统(system-on-a-chip,SoC)工作过程中多个处理器核需要同时访问外部存储器的问题,设计了一种支持片内多运算单元并行访问同一外部存储器的接口结构。该并行访存控制器利用外部存储器与单个运算单元间的带宽差异实现并行访存,针对任务访存特点,采用多种并行访存方式,使用两级仲裁结构对任务进行仲裁。经测试,在使用DDR3作为外部存储器时,满载情况下,该并行访存控制器对外部存储器的平均带宽利用率最高能够达到84.738%,实际任务执行过程中平均带宽利用率最高能够达到54.653%。With the current continuous increase in the bandwidth of off-chip memory,in order to solve the problem that multiple processor cores need to access off-chip memory at the same time during the operation of a multi-core system-on-a-chip(SoC),an interface structure that supports multiple on-chip computing units to access the same off-chip memory in parallel is designed.The parallel memory access controller takes advantage of the difference in bandwidth between off-chip memory and a single computing unit to achieve parallel memory access.It uses multiple parallel memory access methods according to the memory access characteristics of the task,and the two-level arbitration structure is used to arbitrate tasks.The test shows that when using DDR3 as off-chip memory,the controller’s average bandwidth utilization of off-chip memory can reach a maximum of 84.738%under full load,and the average bandwidth utilization during actual task execution can reach a maximum of 54.653%.

关 键 词：多核系统 外部存储器 并行访存 时分复用 任务仲裁 

分 类 号：TN402[电子电信—微电子学与固体电子学]