集成式石英谐振加速度计倍频电路设计  

Design of Frequency Doubling Circuit for Integrated Quartz Resonant Accelerometer

作　　者：刘迪 田文杰[1] 金鑫[1] 陈福彬[1] LIU Di;TIAN Wenjie;JIN Xin;CHEN Fubin(Sensor Key Laboratory, Beijing Information Science and Technology University, Beijing 100101, China)

机构地区：[1]北京信息科技大学传感器重点实验室,北京100101

出　　处：《压电与声光》2021年第5期636-639,共4页Piezoelectrics & Acoustooptics

基　　金：北京市自然科学基金重点资助项目(KZ201511232037);现代控制技术教育部重点实验室(北京信息科技大学)基金资助项目;北京信息科技大学促进高校分类发展基金资助项目(20202021A)。

摘　　要：谐振式加速度计可以将加速度转换为频率信号,在导航、姿态控制等加速度计的应用领域,采集信号需要限定在较短时间内,为了满足应用的要求,基于一种单基片集成式石英谐振器,通过现场可编程门阵列(FPGA)实现了一种针对集成式石英谐振加速度计的倍频电路设计方案,包括时钟自适应模块和锁相环。时钟自适应模块根据当前输入信号产生锁相环基准时钟并将输入信号进行倍频。离心机加速度测试结果表明,当测量时间由1 s缩短为0.125 s时,传感器标度因数为3173 Hz/g(g=9.8 m/s2),线性相关系数R2=0.99932,与未倍频时相比,标度因数与线性度基本保持不变,所设计的倍频电路可应用于石英谐振加速度计的信号处理及数据采集系统中。The resonant accelerometer can convert acceleration into frequency signal.In the field of navigation,attitude control and other accelerometer applications,the signal acquisition needs to be limited in a short time.In order to meet the application requirements,based on a quartz resonator on a single substrate,a design scheme of frequency doubling circuit for integrated quartz resonant accelerometer is realized by field programmable gate array(FPGA),including the clock adaptive module and phase-locked loop.The clock adaptive module generates a phase-locked loop reference clock according to the current input signal and multiplies the frequency of the input signal.The centrifuge acceleration test results show that when the measurement time is shortened from 1 s to 0.125 s,the scale factor of the sensor is 3173 Hz/g(g=9.8 m/s2),and the linear correlation coefficient R2=0.99932.Compared with the case without frequency doubling,the scale factor and linearity are basically unchanged.The designed frequency doubling circuit can be used in the signal processing and data acquisition system of quartz resonant accelerometer.

关 键 词：加速度计 集成式石英谐振器 倍频电路 现场可编程门阵列(FPGA) 实时性 

分 类 号：TN384[电子电信—物理电子学] TM22[一般工业技术—材料科学与工程]