基于多核CPU的雷达信号并发处理架构设计  

Design of Radar Signal Concurrency Processing Architecture Based on Multi-core CPU

作　　者：杨思军 YANG Si-jun(The 723 Institute of CSIC,Yangzhou 225101,China)

机构地区：[1]中国船舶重工集团公司第七二三研究所,江苏扬州225101

出　　处：《舰船电子对抗》2021年第5期62-66,共5页Shipboard Electronic Countermeasure

摘　　要：分析了多核中央处理器(CPU)的特点,利用多核CPU的线程池加速处理技术,基于雷达信号处理数据流模式驱动,研究了并发处理的实时雷达信号处理架构。This paper analyzes the characteristics of multi-core central processing unit(CPU),uses thread pool acceleration processing technology based on multi-core CPU,studies the real-time radar signal processing architecture with concurrency processing based on the data stream mode driven of radar signal processing.

关 键 词：并发处理 线程池加速技术 数据流驱动 

分 类 号：TN957.51[电子电信—信号与信息处理]